公开(公告)号：US11854791B2

公开(公告)日：2023-12-26

申请号：US17811193

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/458 ,  H01L21/02236 ,  H01L21/02532 ,  H01L21/02603 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66553 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

公开(公告)号：US20230369504A1

公开(公告)日：2023-11-16

申请号：US18357357

申请日：2023-07-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L23/528 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/285 ,  H01L29/06 ,  H01L29/417 ,  H01L29/45 ,  H01L21/311 ,  H01L21/02

CPC classification number: H01L29/78618 ,  H01L23/5286 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/7848 ,  H01L21/28518 ,  H01L29/0673 ,  H01L29/78696 ,  H01L29/41733 ,  H01L29/45 ,  H01L29/66636 ,  H01L29/66742 ,  H01L21/31116 ,  H01L21/02603

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.

公开(公告)号：US11676819B2

公开(公告)日：2023-06-13

申请号：US17809847

申请日：2022-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Zhi-Chang Lin ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/40 ,  H01L29/10 ,  H01L27/092 ,  H01L29/786 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/3213 ,  H01L21/3105

CPC classification number: H01L21/28123 ,  H01L21/31055 ,  H01L21/32136 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66545

Abstract: A semiconductor device includes a first fin, a second fin, a first gate electrode having a first portion that at least partially wraps around an upper portion of the first fin and a second portion that at least partially wraps around an upper portion of the second fin, a second gate electrode having a portion that at least partially wraps around the upper portion of the first fin, and a gate-cut feature having a first portion in the first gate electrode between the first and second portions of the first gate electrode. The gate-cut feature is at least partially filled with one or more dielectric materials. In a direction of a longitudinal axis of the first fin, the gate-cut feature has a second portion extending to a sidewall of the second gate electrode.

公开(公告)号：US11652043B2

公开(公告)日：2023-05-16

申请号：US17158409

申请日：2021-01-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang ,  Yu-Xuan Huang

IPC: H01L23/522 ,  H01L21/768 ,  H01L27/088

CPC classification number: H01L23/5226 ,  H01L21/76802 ,  H01L27/088

Abstract: An integrated circuit (IC) structure includes a gate structure, a source epitaxial structure, a drain epitaxial structure, a front-side interconnection structure, a backside dielectric layer, an epitaxial regrowth layer, and a backside via. The source epitaxial structure and the drain epitaxial structure are respectively on opposite sides of the gate structure. The front-side interconnection structure is over a front-side of the source epitaxial structure and a front-side of the drain epitaxial structure. The backside dielectric layer is over a backside of the source epitaxial structure and a backside of the drain epitaxial structure. The epitaxial regrowth layer is on the backside of a first one of the source epitaxial structure and the drain epitaxial structure. The backside via extends through the backside dielectric layer and overlaps the epitaxial regrowth layer.

公开(公告)号：US11581410B2

公开(公告)日：2023-02-14

申请号：US17174793

申请日：2021-02-12

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Pei-Yu Wang ,  Chi On Chui

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/06 ,  H01L29/423 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/775 ,  H01L29/786 ,  H01L21/3065 ,  H01L21/306

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain (LDD) region, the first LDD region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first LDD region; an interlayer dielectric (ILD) layer over the first epitaxial source/drain region; a source/drain contact extending through the ILD layer, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

公开(公告)号：US11532703B2

公开(公告)日：2022-12-20

申请号：US17127095

申请日：2020-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Huan-Chieh Su ,  Cheng-Chi Chuang ,  Shang-Wen Chang ,  Yi-Hsun Chiu ,  Pei-Yu Wang ,  Ching-Wei Tsai ,  Chih-Hao Wang

IPC: H01L29/06 ,  H01L27/092 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L23/538

Abstract: In an embodiment, a device includes: a power rail contact; an isolation region on the power rail contact; a first dielectric fin on the isolation region; a second dielectric fin adjacent the isolation region and the power rail contact; a first source/drain region on the second dielectric fin; and a source/drain contact between the first source/drain region and the first dielectric fin, the source/drain contact contacting a top surface of the first source/drain region, a side surface of the first source/drain region, and a top surface of the power rail contact.

公开(公告)号：US20220352339A1

公开(公告)日：2022-11-03

申请号：US17811193

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang

IPC: H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

公开(公告)号：US11424338B2

公开(公告)日：2022-08-23

申请号：US16836320

申请日：2020-03-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Pei-Yu Wang

IPC: H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/311 ,  H01L29/423 ,  H01L29/786

Abstract: A semiconductor device according to the present disclosure includes a vertical stack of channel members, a gate structure over and around the vertical stack of channel members, and a first source/drain feature and a second source/drain feature. Each of the vertical stack of channel members extends along a first direction between the first source/drain feature and the second source/drain feature. Each of the vertical stack of channel members is spaced apart from the first source/drain feature by a silicide feature.

公开(公告)号：US11195930B1

公开(公告)日：2021-12-07

申请号：US16936233

申请日：2020-07-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Yuan Chen ,  Pei-Yu Wang ,  Huan-Chieh Su ,  Chih-Hao Wang

IPC: H01L21/28 ,  H01L23/535 ,  H01L29/40 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

Abstract: The present disclosure relates to a semiconductor device having a backside source/drain contact, and method for forming the device. The semiconductor device includes a source/drain feature having a top surface and a bottom surface, a first silicide layer formed in contact with the top surface of the source/drain feature, a first conductive feature formed on the first silicide layer, and a second conductive feature having a body portion and a first sidewall portion extending from the body portion, wherein the body portion is below the bottom surface of the source/drain feature, and the first sidewall portion is in contact with the first conductive feature.

公开(公告)号：US20210336063A1

公开(公告)日：2021-10-28

申请号：US16998576

申请日：2020-08-20

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yi-Bo Liao ,  Yu-Xuan Huang ,  Pei-Yu Wang ,  Cheng-Ting Chung ,  Ching-Wei Tsai ,  Hou-Yu Chen

IPC: H01L29/786 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H01L29/417 ,  H01L29/45 ,  H01L29/78 ,  H01L21/02 ,  H01L21/311 ,  H01L21/285 ,  H01L29/66

Abstract: In an embodiment, a device includes: a first interconnect structure including metallization patterns; a second interconnect structure including a power rail; a device layer between the first interconnect structure and the second interconnect structure, the device layer including a first transistor, the first transistor including an epitaxial source/drain region; and a conductive via extending through the device layer, the conductive via connecting the power rail to the metallization patterns, the conductive via contacting the epitaxial source/drain region.