公开(公告)号：US10276691B2

公开(公告)日：2019-04-30

申请号：US15653720

申请日：2017-07-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L21/225 ,  H01L21/265 ,  H01L29/66 ,  H01L29/165

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US09425317B1

公开(公告)日：2016-08-23

申请号：US14632987

申请日：2015-02-26

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Tsung-Yao Wen ,  Yao-De Chiou ,  Sheng-Chen Wang ,  Sai-Hooi Yeong

IPC: H01L29/78 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/7856 ,  H01L21/823487 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851

Abstract: A fin field effect transistor (FinFET) device structure and method for forming the same are provided. The FinFET device structure includes a substrate and a fin structure extending above the substrate. The FinFET device structure includes an isolation structure, and the fin structure is embedded in the isolation structure. The FinFET device structure also includes a gate structure formed on a middle portion of the fin structure. The gate structure has a top portion and bottom portion, and the bottom portion is wider than the top portion. The FinFET device structure further includes a source/drain (S/D) structure formed adjacent to the gate structure.

Abstract translation: 提供了鳍状场效应晶体管（FinFET）器件结构及其形成方法。 FinFET器件结构包括在衬底上延伸的衬底和鳍结构。 FinFET器件结构包括隔离结构，鳍结构嵌入在隔离结构中。 FinFET器件结构还包括形成在鳍结构的中间部分上的栅极结构。 栅极结构具有顶部和底部，并且底部部分比顶部部分宽。 FinFET器件结构还包括与栅极结构相邻形成的源/漏（S / D）结构。

公开(公告)号：US12200940B2

公开(公告)日：2025-01-14

申请号：US17874815

申请日：2022-07-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Chung-Te Lin ,  Feng-Cheng Yang ,  Meng-Han Lin ,  Sheng-Chen Wang

IPC: H10B51/20 ,  G11C11/22 ,  G11C11/56 ,  H01L29/66 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30 ,  H01L21/28

Abstract: In an embodiment, a device includes: a first dielectric layer over a substrate; a word line over the first dielectric layer, the word line including a first main layer and a first glue layer, the first glue layer extending along a bottom surface, a top surface, and a first sidewall of the first main layer; a second dielectric layer over the word line; a first bit line extending through the second dielectric layer and the first dielectric layer; and a data storage strip disposed between the first bit line and the word line, the data storage strip extending along a second sidewall of the word line.

公开(公告)号：US12167608B2

公开(公告)日：2024-12-10

申请号：US17981608

申请日：2022-11-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Yu-Ming Lin ,  Chung-Te Lin

IPC: H10B51/20 ,  G11C11/22 ,  H01L23/522 ,  H01L29/66 ,  H01L29/78 ,  H10B43/20 ,  H10B43/27 ,  H10B51/10 ,  H10B51/30

Abstract: In an embodiment, a device includes: a source line extending in a first direction; a bit line extending in the first direction; a back gate between the source line and the bit line, the back gate extending in the first direction; a channel layer surrounding the back gate; a word line extending in a second direction, the second direction perpendicular to the first direction; and a data storage layer extending along the word line, the data storage layer between the word line and the channel layer, the data storage layer between the word line and the bit line, the data storage layer between the word line and the source line.

公开(公告)号：US20240312830A1

公开(公告)日：2024-09-19

申请号：US18673571

申请日：2024-05-24

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Han-Jong Chia ,  Meng-Han Lin ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Chung-Te Lin

IPC: H01L21/762 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

CPC classification number: H01L21/76237 ,  G11C7/18 ,  H10B51/20 ,  H10B99/00

Abstract: A method of forming a three-dimensional (3D) memory device includes: forming a layer stack over a substrate, the layer stack including alternating layers of a first dielectric material and a second dielectric material; forming trenches extending through the layer stack; replacing the second dielectric material with an electrically conductive material to form word lines (WLs); lining sidewalls and bottoms of the trenches with a ferroelectric material; filling the trenches with a third dielectric material; forming bit lines (BLs) and source lines (SLs) extending vertically through the third dielectric material; removing portions of the third dielectric material to form openings in the third dielectric material between the BLs and the SLs; forming a channel material along sidewalls of the openings; and filling the openings with a fourth dielectric.

公开(公告)号：US20240268122A1

公开(公告)日：2024-08-08

申请号：US18638140

申请日：2024-04-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Bo-Feng Young ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  G11C7/18 ,  G11C11/14 ,  H10B51/10

CPC classification number: H10B51/20 ,  G11C7/18 ,  G11C11/14 ,  H10B51/10

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

公开(公告)号：US20240260276A1

公开(公告)日：2024-08-01

申请号：US18612267

申请日：2024-03-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd

Inventor： Sheng-Chen Wang ,  Kai-Hsuan Lee ,  Sai-Hooi Yeong ,  Chi On Chui

IPC: H10B51/20 ,  H01L29/06 ,  H01L29/78 ,  H10B51/10

CPC classification number: H10B51/20 ,  H01L29/0649 ,  H01L29/78391 ,  H10B51/10

Abstract: A device includes a semiconductor substrate; a word line extending over the semiconductor substrate; a memory film extending along the word line, wherein the memory film contacts the word line; a channel layer extending along the memory film, wherein the memory film is between the channel layer and the word line; source lines extending along the memory film, wherein the memory film is between the source lines and the word line; bit lines extending along the memory film, wherein the memory film is between the bit lines and the word line; and isolation regions, wherein each isolation region is between a source line and a bit line, wherein each of the isolation regions includes an air gap and a seal extending over the air gap.

公开(公告)号：US11997855B2

公开(公告)日：2024-05-28

申请号：US17109427

申请日：2020-12-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Feng Young ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Yu-Ming Lin ,  Mauricio Manfrini ,  Han-Jong Chia

IPC: H10B63/00 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  H10B61/00

CPC classification number: H10B63/30 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/7869 ,  H10B61/22

Abstract: The present disclosure, in some embodiments, relates to a memory device. In some embodiments, the memory device has a substrate and a lower interconnect metal line disposed over the substrate. The memory device also has a selector channel disposed over the lower interconnect metal line and a selector gate electrode wrapping around a sidewall of the selector channel and separating from the selector channel by a selector gate dielectric. The memory device also has a memory cell disposed over and electrically connected to the selector channel and an upper interconnect metal line disposed over the memory cell. By placing the selector within the back-end interconnect structure, front-end space is saved, and more integration flexibility is provided.

公开(公告)号：US11991886B2

公开(公告)日：2024-05-21

申请号：US18151682

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Meng-Han Lin ,  Bo-Feng Young ,  Han-Jong Chia ,  Sheng-Chen Wang ,  Feng-Cheng Yang ,  Sai-Hooi Yeong ,  Yu-Ming Lin

IPC: H10B51/20 ,  G11C7/18 ,  G11C11/14 ,  H10B51/10

CPC classification number: H10B51/20 ,  G11C7/18 ,  G11C11/14 ,  H10B51/10

Abstract: A method of forming a ferroelectric random access memory (FeRAM) device includes: forming a first layer stack and a second layer stack successively over a substrate, where the first layer stack and the second layer stack have a same layered structure that includes a layer of a first electrically conductive material over a layer of a first dielectric material, where the first layer stack extends beyond lateral extents of the second layer stack; forming a trench that extends through the first layer stack and the second layer stack; lining sidewalls and a bottom of the trench with a ferroelectric material; conformally forming a channel material in the trench over the ferroelectric material; filling the trench with a second dielectric material; forming a first opening and a second opening in the second dielectric material; and filling the first opening and the second opening with a second electrically conductive material.

公开(公告)号：US20240098959A1

公开(公告)日：2024-03-21

申请号：US18517275

申请日：2023-11-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kai-Hsuan Lee ,  Chia-Ta Yu ,  Cheng-Yu Yang ,  Sheng-Chen Wang ,  Sai-Hooi Yeong ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H10B10/00 ,  H01L21/027 ,  H01L21/306 ,  H01L21/311 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/66

CPC classification number: H10B10/12 ,  H01L21/0273 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/6656 ,  H01L29/66636 ,  H10B10/18 ,  H01L29/165

Abstract: A method includes etching a first semiconductor fin and a second semiconductor fin to form first recesses. The first and the second semiconductor fins have a first distance. A third semiconductor fin and a fourth semiconductor fin are etched to form second recesses. The third and the fourth semiconductor fins have a second distance equal to or smaller than the first distance. An epitaxy is performed to simultaneously grow first epitaxy semiconductor regions from the first recesses and second epitaxy semiconductor regions from the second recesses. The first epitaxy semiconductor regions are merged with each other, and the second epitaxy semiconductor regions are separated from each other.