公开(公告)号：US11139341B2

公开(公告)日：2021-10-05

申请号：US16379901

申请日：2019-04-10

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-An Liu ,  Chung-Cheng Wu ,  Harry-Hak-Lay Chuang ,  Gwan-Sin Chang ,  Tien-Wei Chiang ,  Zhiqiang Wu ,  Chia-Hsiang Chen

IPC: H01L27/22 ,  H01L43/08 ,  H01L43/02 ,  G11C11/16

Abstract: In some embodiments, the present application provides a memory device. The memory device includes a chip that includes a magnetic random access memory (MRAM) cell. A magnetic-field-shielding structure comprised of conductive or magnetic material at least partially surrounds the chip. The magnetic-field-shielding structure comprises a sidewall region that laterally surrounds the chip, an upper region extending upward from the sidewall region, and a lower region extending downward from the sidewall region. At least one of the upper region and/or lower region terminate at an opening over the chip.

公开(公告)号：US11081153B2

公开(公告)日：2021-08-03

申请号：US16395571

申请日：2019-04-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Gaurav Gupta ,  Zhiqiang Wu ,  William J. Gallagher

IPC: G11C11/16 ,  H01L43/12 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

Abstract: In some embodiments, the present application provides a magnetic memory device. The magnetic memory device comprises a bottom electrode, and a first synthetic anti-ferromagnetic (SyAF) layer including a first pinning layer and a second pinning layer disposed over the bottom electrode and having opposite magnetization directions and separated by a first spacer layer. The magnetic memory device further comprises a reference layer disposed over the first pair of pinning layers and a free layer disposed over the reference layer and separated from the reference layer by a tunneling barrier layer. The magnetic memory device further comprises a second synthetic anti-ferromagnetic (SyAF) layer including a third pinning layer and a fourth pinning layer disposed over the free layer and having opposite magnetization directions and separated by a second spacer layer.

公开(公告)号：US20190245089A1

公开(公告)日：2019-08-08

申请号：US16390373

申请日：2019-04-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/08 ,  H01L21/265 ,  H01L29/10

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. In some embodiments, the present disclosure relates to a finFET device and its formation. A strain-inducing layer is disposed on a semiconductor fin between a channel region and a metal gate electrode. First and second inner spacers are disposed on a top surface of the strain-inducing layer and have inner sidewalls disposed along outer sidewalls of the metal gate electrode. First and second outer spacers have innermost sidewalls disposed along outer sidewalls of the first and second inner spacers, respectively. The first and second outer spacers cover outer sidewalls of the first and second inner spacers.

公开(公告)号：US20190097147A1

公开(公告)日：2019-03-28

申请号：US16201742

申请日：2018-11-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Chun-Chieh LU ,  Yu-Ming LIN ,  Ken-Ichi GOTO ,  Jean-Pierre COLINGE ,  Zhiqiang Wu

IPC: H01L51/05 ,  H01L51/00 ,  H01L51/10

Abstract: In a method of manufacturing a gate-all-around field effect transistor, a trench is formed over a substrate. Nano-tube structures are arranged into the trench, each of which includes a carbon nanotube (CNT) having a gate dielectric layer wrapping around the CNT and a gate electrode layer over the gate dielectric layer. An anchor layer is formed in the trench. A part of the anchor layer is removed at a source/drain (S/D) region. The gate electrode layer and the gate dielectric layer are removed at the S/D region, thereby exposing a part of the CNT at the S/D region. An S/D electrode layer is formed on the exposed part of the CNT. A part of the anchor layer is removed at a gate region, thereby exposing a part of the gate electrode layer of the gate structure. A gate contact layer is formed on the exposed part of the gate electrode layer.

公开(公告)号：US20190006391A1

公开(公告)日：2019-01-03

申请号：US15800390

申请日：2017-11-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzer-Min Shen ,  Zhiqiang Wu ,  Chung-Cheng Wu ,  Ching-Wei Tsai ,  Kuan-Lun Cheng ,  Chih-Hao Wang ,  Min Cao

IPC: H01L27/12 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L21/762

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate having a first region and a second region; a first fin active region of a first semiconductor material disposed within the first region, oriented in a first direction, wherein the first fin active region has a crystalline direction along the first direction; and a second fin active region of a second semiconductor material disposed within the second region and oriented in the first direction, wherein the second fin active region has a crystalline direction along the first direction.

公开(公告)号：US20160365447A1

公开(公告)日：2016-12-15

申请号：US15247024

申请日：2016-08-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Zhiqiang Wu ,  Yi-Ming Sheu ,  Tzer-Min Shen ,  Chun-Fu Cheng ,  Hong-Shen Chen

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/08

CPC classification number: H01L29/7848 ,  H01L21/26586 ,  H01L29/0615 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66598 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785 ,  H01L29/7851

Abstract: The demand for increased performance and shrinking geometry from ICs has brought the introduction of multi-gate devices including finFET devices. Inducing a higher tensile strain/stress in a region provides for enhanced electron mobility, which may improve performance. High temperature processes during device fabrication tend to relax the stress on these strain inducing layers. The present disclosure relates to a method of forming a strain inducing layer or cap layer at the RPG (replacement poly silicon gate) stage of a finFET device formation process. In some embodiments, the strain inducing layer is doped to reduce the external resistance.

Abstract translation: IC的性能提升和几何尺寸的需求引起了包括finFET器件在内的多栅极器件的引入。 在区域中诱导更高的拉伸应变/应力提供增强的电子迁移率，这可以提高性能。 器件制造期间的高温工艺往往会使这些应变诱导层的应力松弛。 本公开涉及在finFET器件形成工艺的RPG（替代多晶硅栅极）级形成应变诱导层或覆盖层的方法。 在一些实施例中，应变诱导层被掺杂以减小外部电阻。

公开(公告)号：US09224814B2

公开(公告)日：2015-12-29

申请号：US14156515

申请日：2014-01-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsung-Hsing Yu ,  Chia-Wen Liu ,  Yeh Hsu ,  Shih-Syuan Huang ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/306 ,  H01L21/265 ,  H01L21/02 ,  H01L29/16

CPC classification number: H01L29/7836 ,  H01L21/02238 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/30604 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/161 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

Abstract: The present disclosure relates to a method of forming a transistor device having a carbon implantation region that provides for a low variation of voltage threshold, and an associated apparatus. The method is performed by forming a well region within a semiconductor substrate. The semiconductor substrate is selectively etched to form a recess within the well region. After formation of the recess, a carbon implantation is selectively performed to form a carbon implantation region within the semiconductor substrate at a position underlying the recess. An epitaxial growth is then performed to form one or more epitaxial layers within the recess at a position overlying the carbon implantation region. Source and drain regions are subsequently formed within the semiconductor substrate such that a channel region, comprising the one or more epitaxial layers, separates the source/drains from one another.

Abstract translation: 本公开涉及一种形成具有提供电压阈值的低变化的碳注入区域的晶体管器件的方法和相关联的器件。 该方法通过在半导体衬底内形成阱区进行。 选择性地蚀刻半导体衬底以在阱区内形成凹陷。 在形成凹部之后，选择性地进行碳注入，以在凹部下方的位置在半导体衬底内形成碳注入区域。 然后进行外延生长以在覆盖碳注入区域的位置处在凹槽内形成一个或多个外延层。 源极和漏极区域随后形成在半导体衬底内，使得包括一个或多个外延层的沟道区域将源极/漏极彼此分离。

公开(公告)号：US08981479B2

公开(公告)日：2015-03-17

申请号：US14108391

申请日：2013-12-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Ching-Fang Huang ,  Wen-Hsing Hsieh ,  Tsung-Hsing Yu ,  Yi-Ming Sheu ,  Ken-Ichi Goto ,  Zhiqiang Wu

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L27/092 ,  H01L29/66

CPC classification number: H01L29/7855 ,  H01L21/823431 ,  H01L21/823821 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/66795 ,  H01L29/785

Abstract: A multi-gate semiconductor device and method for forming the same. A multi-gate semiconductor device is formed including a first fin of a first transistor formed on a semiconductor substrate having a first dopant type. The first transistor has a doped channel region of the first dopant type. The device also includes a second fin of a second transistor formed on the first dopant type semiconductor substrate. The second transistor has a doped channel region of a second dopant type. The device further includes a gate electrode layer of the second dopant type formed over the channel region of the first fin and a gate electrode layer of the first dopant type formed over the channel region of the second fin.

Abstract translation: 一种多栅半导体器件及其制造方法。 形成多栅半导体器件，其包括形成在具有第一掺杂剂类型的半导体衬底上的第一晶体管的第一鳍。 第一晶体管具有第一掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一掺杂剂型半导体衬底上的第二晶体管的第二鳍。 第二晶体管具有第二掺杂剂类型的掺杂沟道区。 该器件还包括形成在第一鳍片的沟道区域上的第二掺杂剂类型的栅极电极层和形成在第二鳍片的沟道区域上的第一掺杂剂类型的栅极电极层。

公开(公告)号：US12300754B2

公开(公告)日：2025-05-13

申请号：US18190754

申请日：2023-03-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Zhiqiang Wu

IPC: H01L29/786 ,  H01L29/423

Abstract: Multi-gate devices and methods for fabricating such are disclosed herein. An exemplary device includes a channel layer, a first source/drain feature, a second source/drain feature, and a metal gate. The channel layer has a first horizontal segment, a second horizontal segment, and a vertical segment connects the first horizontal segment and the second horizontal segment. The first horizontal segment and the second horizontal segment extend along a first direction, and the vertical segment extends along a second direction. The vertical segment has a width along the first direction and a thickness along the second direction, and the thickness is greater than the width. The channel layer extends between the first source/drain feature and the second source/drain feature along a third direction. The metal gate wraps channel layer. In some embodiments, the first horizontal segment and the second horizontal segment are nanosheets.

公开(公告)号：US20240194764A1

公开(公告)日：2024-06-13

申请号：US18444918

申请日：2024-02-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Ching Wang ,  Jon-Hsu Ho ,  Wen-Hsing Hsieh ,  Kuan-Lun Cheng ,  Chung-Wei Wu ,  Zhiqiang Wu

IPC: H01L29/66 ,  H01L21/8234 ,  H01L29/78

CPC classification number: H01L29/66484 ,  H01L21/823418 ,  H01L21/823431 ,  H01L29/66553 ,  H01L29/66795 ,  H01L29/7831 ,  H01L29/7848

Abstract: A semiconductor device includes semiconductor channel members disposed over a substrate, a gate dielectric layer disposed on and wrapping around the semiconductor channel members, a gate electrode layer disposed on the gate dielectric layer and wrapping around the semiconductor channel members, a source/drain (S/D) epitaxial layer in physical contact with the semiconductor channel members, and a dielectric spacer interposing the S/D epitaxial layer and the gate dielectric layer. The dielectric spacer includes a first dielectric layer in physical contact with the gate dielectric layer and a second dielectric layer in physical contact with the first dielectric layer. The first dielectric layer has a dielectric constant higher than that of the second dielectric layer. The second dielectric layer separates the first dielectric layer from physically contacting the S/D epitaxial layer.