公开(公告)号：US11069807B2

公开(公告)日：2021-07-20

申请号：US16515898

申请日：2019-07-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Cheng-Ming Lin ,  Sai-Hooi Yeong ,  Ziwei Fang ,  Bo-Feng Young ,  Chi On Chui ,  Chih-Yu Chang ,  Huang-Lin Chao

IPC: H01L21/02 ,  H01L29/66 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28

Abstract: The present disclosure relates to a semiconductor device includes a substrate and first and second spacers on the substrate. The semiconductor device includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers. The first portion includes a crystalline material and the second portion comprises an amorphous material. The gate stack further includes a gate electrode on the first and second portions of the gate dielectric layer.

公开(公告)号：US20210166969A1

公开(公告)日：2021-06-03

申请号：US17176052

申请日：2021-02-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chung-Liang Cheng ,  Ziwei Fang

IPC: H01L21/768 ,  H01L29/78 ,  H01L23/522 ,  H01L23/532

Abstract: A semiconductor structure includes a metal gate structure disposed over a semiconductor substrate, an interlayer dielectric (ILD) layer disposed over the metal gate structure, and a gate contact disposed in the ILD layer and over the metal gate structure, where a bottom surface of the gate contact is defined by a barrier layer disposed over the metal gate structure, where sidewall surfaces of the gate contact are defined by and directly in contact with the ILD layer, and where the barrier layer is free of nitrogen.

公开(公告)号：US20210134985A1

公开(公告)日：2021-05-06

申请号：US17121007

申请日：2020-12-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sai-Hooi Yeong ,  Sheng-Chen Wang ,  Bo-Yu Lai ,  Ziwei Fang ,  Feng-Cheng Yang ,  Yen-Ming Chen

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/225 ,  H01L29/165

Abstract: Doping techniques for fin-like field effect transistors (FinFETs) are disclosed herein. An exemplary method includes forming a fin structure, forming a doped amorphous layer over a portion of the fin structure, and performing a knock-on implantation process to drive a dopant from the doped amorphous layer into the portion of the fin structure, thereby forming a doped feature. The doped amorphous layer includes a non-crystalline form of a material. In some implementations, the knock-on implantation process crystallizes at least a portion of the doped amorphous layer, such that the portion of the doped amorphous layer becomes a part of the fin structure. In some implementations, the doped amorphous layer includes amorphous silicon, and the knock-on implantation process crystallizes a portion of the doped amorphous silicon layer.

公开(公告)号：US20200381529A1

公开(公告)日：2020-12-03

申请号：US16994865

申请日：2020-08-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun-Hsiung Tsai ,  Kuo-Feng Yu ,  Chien-Tai Chan ,  Ziwei Fang ,  Kei-Wei Chen ,  Huai-Tei Yang

IPC: H01L29/49 ,  H01L21/225 ,  H01L29/66 ,  H01L29/78

Abstract: A gate structure, a semiconductor device, and the method of forming a semiconductor device are provided. In various embodiments, the gate structure includes a gate stack and a doped spacer overlying a sidewall of the gate stack. The gate stack contains a doped work function metal (WFM) stack and a metal gate electrode overlying the doped WFM stack.

公开(公告)号：US10854729B2

公开(公告)日：2020-12-01

申请号：US16578360

申请日：2019-09-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tsan-Chun Wang ,  Ziwei Fang ,  Chii-Horng Li ,  Tze-Liang Lee ,  Chao-Cheng Chen ,  Syun-Ming Jang

IPC: H01L29/66 ,  H01L29/10 ,  H01L29/165 ,  H01L21/8238 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/265

Abstract: The present disclosure relates to a method of forming a transistor device. In this method, first and second well regions are formed within a semiconductor substrate. The first and second well regions have first and second etch rates, respectively, which are different from one another. Dopants are selectively implanted into the first well region to alter the first etch rate to make the first etch rate substantially equal to the second etch rate. The first, selectively implanted well region and the second well region are etched to form channel recesses having equal recess depths. An epitaxial growth process is performed to form one or more epitaxial layers within the channel recesses.

公开(公告)号：US10854503B2

公开(公告)日：2020-12-01

申请号：US16262235

申请日：2019-01-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hung-Chang Sun ,  Akira Mineji ,  Ziwei Fang

IPC: H01L21/764 ,  H01L29/51 ,  H01L29/66 ,  H01L21/265 ,  H01L21/311 ,  H01L21/3105 ,  H01L21/266

Abstract: The present disclosure provides a method of fabricating a semiconductor structure in accordance with some embodiments. The method includes receiving a substrate having an active region and an isolation region; forming gate stacks on the substrate and extending from the active region to the isolation region; forming an inner gate spacer and an outer gate spacer on sidewalls of the gate stacks; forming an interlevel dielectric (ILD) layer on the substrate; removing the outer gate spacer in the isolation region, resulting in an air gap between the inner gate spacer and the ILD layer; and performing an ion implantation process to the ILD layer, thereby expanding the ILD layer to cap the air gap.

公开(公告)号：US10685884B2

公开(公告)日：2020-06-16

申请号：US15665230

申请日：2017-07-31

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yasutoshi Okuno ,  Cheng-Yi Peng ,  Ziwei Fang ,  I-Ming Chang ,  Akira Mineji ,  Yu-Ming Lin ,  Meng-Hsuan Hsiao

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/78 ,  H01L21/203 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/165 ,  H01L27/12 ,  H01L21/84 ,  H01L29/161

Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a channel region and a source/drain region disposed adjacent to the channel region. The FET also includes a gate electrode disposed over the channel region. The FET is an n-type FET and the channel region is made of Si. The source/drain region includes an epitaxial layer including Si1-x-yM1xM2y, where M1 is one or more of Ge and Sn, and M2 is one or more of P and As, and 0.01≤x≤0.1.

公开(公告)号：US10115624B2

公开(公告)日：2018-10-30

申请号：US15197984

申请日：2016-06-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： De-Wei Yu ,  Tsu-Hsiu Perng ,  Ziwei Fang

IPC: H01L21/762 ,  H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/78

Abstract: A method of semiconductor device fabrication includes providing a substrate having a hardmask layer thereover. The hardmask layer is patterned to expose the substrate. The substrate is etched through the patterned hardmask layer to form a first fin element and a second fin element extending from the substrate. An isolation feature between the first and second fin elements is formed, where the isolation feature has a first etch rate in a first solution. A laser anneal process is performed to irradiate the isolation feature with a pulsed laser beam. A pulse duration of the pulsed laser beam is adjusted based on a height of the isolation feature. The isolation feature after performing the laser anneal process has a second etch rate less than the first etch rate in the first solution.

公开(公告)号：US10049918B2

公开(公告)日：2018-08-14

申请号：US15395310

申请日：2016-12-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Cheng Hung ,  Ru-Gun Liu ,  Wei-Liang Lin ,  Ta-Ching Yu ,  Yung-Sung Yen ,  Ziwei Fang ,  Tsai-Sheng Gau ,  Chin-Hsiang Lin ,  Kuei-Shun Chen

IPC: H01L21/311 ,  H01L21/768 ,  H01L21/033 ,  H01L21/3115

Abstract: Directional patterning methods are disclosed herein. An exemplary method includes performing a lithography process to form a pattered hard mask layer over a wafer, wherein the patterned hard mask layer includes a hard mask feature having an associated horizontally-defined characteristic; tuning an etching process to direct etching species in a substantially horizontal direction relative to a horizontal surface of the wafer, such that the etching process horizontally removes portions of the patterned hard mask layer, thereby modifying the horizontally-defined characteristic of the hard mask feature; and forming an integrated circuit feature that corresponds with the hard mask feature having the modified horizontally-defined characteristic. Horizontally-defined characteristic can include a length, a width, a line edge roughness, a line width roughness, a line end profile, other horizontally-defined characteristics, or combinations thereof. In some implementations, the directional patterning method disclosed herein can achieve oblique interconnects and/or slot (rectangular) via interconnects.

公开(公告)号：US10002867B2

公开(公告)日：2018-06-19

申请号：US15062210

申请日：2016-03-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chun Hsiung Tsai ,  Ziwei Fang ,  Tsan-Chun Wang ,  Kei-Wei Chen

IPC: H01L27/088 ,  H01L29/06 ,  H01L29/08 ,  H01L21/8234 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L21/311

CPC classification number: H01L27/0886 ,  H01L21/30604 ,  H01L21/31116 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848 ,  H01L29/785

Abstract: A fin-type field effect transistor comprising a substrate, at least one gate stack and epitaxy material portions is described. The substrate has fins and insulators located between the fins, and the fins include channel portions and flank portions beside the channel portions. The at least one gate stack is disposed over the insulators and over the channel portions of the fins. The epitaxy material portions are disposed over the flank portions of the fins and at two opposite sides of the at least one gate stack. The epitaxy material portions disposed on the flank portions of the fins are separate from one another.