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    Semiconductor device having identification number, manufacturing method thereof and electronic device
    41.
    发明授权
    Semiconductor device having identification number, manufacturing method thereof and electronic device 有权
    具有识别号码的半导体装置及其制造方法以及电子装置

    公开(公告)号：US06617172B2

    公开(公告)日：2003-09-09

    申请号：US09942612

    申请日：2001-08-31

    申请人： Mitsuo Usami

    发明人： Mitsuo Usami

    IPC分类号： H01L2100

    CPC分类号： H01L23/544 ,  H01L2223/54413 ,  H01L2223/54433 ,  H01L2223/54473 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention aims to economically implement an ultra-compact semiconductor device having an identification number according to the efficient utilization of an electron-beam writing method. A memory for identifying a 128-bit identification number, which makes use of a transistor, is configured by each contact hole selectively defined by an electron-beam writing method. A plane long-side size of a semiconductor chip is set to 0.5 mm or less. The contact holes are defined simultaneously with contact holes for peripheral circuits. In addition, the plane long-side size of the semiconductor chip is set smaller than the thickness of a wafer prior to the start of its manufacture and set larger than the thickness of the post-thinning wafer. Otherwise, the same data as a barcode is further stored in the memory. Additionally, data obtained by enciphering the identification number is used to test or inspect the semiconductor chip.

    摘要翻译： 本发明旨在经济地实现具有根据电子束写入方法的有效利用的识别号的超小型半导体器件。一种用于识别利用晶体管的128位识别号码的存储器被配置 通过由电子束写入方法选择性地限定的每个接触孔。 将半导体芯片的平面长边尺寸设定为0.5mm以下。 接触孔与外围电路的接触孔同时定义。 此外，将半导体芯片的平面长边尺寸设定为小于其制造开始之前的晶片的厚度，并将其设定为大于后变薄晶片的厚度。 否则，与条形码相同的数据进一步存储在存储器中。 此外，通过加密识别号码获得的数据用于测试或检查半导体芯片。

    Semiconductor device
    42.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06588672B1

    公开(公告)日：2003-07-08

    申请号：US09463626

    申请日：2000-01-28

    申请人： Mitsuo Usami

    发明人： Mitsuo Usami

    IPC分类号： G06K1906

    CPC分类号： G06K19/073 ,  G06K19/07372 ,  G06Q20/341 ,  G06Q20/4097 ,  G07F7/086 ,  G07F7/1008 ,  G09C1/00 ,  H01L23/576 ,  H01L2224/13 ,  H04L9/3278 ,  H04L2209/12

    摘要： A semiconductor device is provided which effectively prevents forgery or alteration of IC cards or the like handling important information. Electrodes each having an unshaped irregular surface are provided, respectively, on the IC chip side and the substrate side. The electrodes are connected to each other, with the IC chip facing downward. Connection resistance is employed as a Key code by subjecting the capacitance between the electrodes to A/D conversion. This serves to prevent the duplication of IC cards or the like by employing the connection resistance having a random value as the key code of cryptograph.

    摘要翻译： 提供了一种半导体器件，其有效地防止伪造或改变处理重要信息的IC卡等。 分别在IC芯片侧和基板侧设置具有不规则的不规则表面的电极。 电极彼此连接，IC芯片朝下。 通过使电极之间的电容进行A / D转换，将连接电阻用作键码。 这用于通过采用具有随机值的连接电阻作为密码的关键码来防止IC卡等的复制。

    Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions
    48.
    发明授权
    Semiconductor integrated circuit device with a plurality of logic circuits having active pull-down functions 失效
    具有多个具有主动下拉功能的逻辑电路的半导体集成电路器件

    公开(公告)号：US5298802A

    公开(公告)日：1994-03-29

    申请号：US56798

    申请日：1993-05-03

    申请人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

    发明人： Mitsuo Usami ,  Noboru Shiozawa ,  Toshio Yamada ,  Hiromasa Katoh ,  Kazuyoshi Satoh ,  Tohru Kobayashi ,  Tatsuya Kimura ,  Masato Hamamoto ,  Atsushi Shimizu ,  Kaoru Koyu

    IPC分类号： H03K3/2885 ,  H03K17/0412 ,  H03K17/66 ,  H03K19/013 ,  H03K19/086

    CPC分类号： H03K19/086 ,  H03K17/04126 ,  H03K17/666 ,  H03K19/0136 ,  H03K3/2885

    摘要： In accordance with one aspect of the invention, a semiconductor integrated circuit is provided wherein an input circuit is formed by a phase split circuit having a bipolar transistor which outputs an inverted output from the collector and a non-inverted output from the emitter. The emitter follower output circuit is driven by an inverted output of the phase split circuit. Meanwhile, an emitter load of the emitter follower output circuit is formed by a transistor, and the emitter load transistor is temporarily driven conductively by a charging current of the capacitance to be charged by the rising edge of the non-inverted output of the phase split circuit. As a second aspect of the invention, a logic circuit is formed of a logic portion and an output portion. The output portion includes an emitter follower output transistor receiving an output signal generated by the logic portion and an active pull-down transistor receiving at its base a signal supplied thereto through a capacitance element. The signal received by the active pull-down transistor has a phase reverse to that of the input signal supplied to the base of said output transistor. Between the base and emitter of the active pull-down transistor, there is disposed a bias circuit formed of a transistor receiving at its base a predetermined bias voltage and an emitter resistor. Further, between a junction point of the emitter follower output transistor and the active pull-down transistor and the emitter of the transistor as a constituent of the bias circuit, there is disposed a capacitance element for feeding back the output signal.

    摘要翻译： 根据本发明的一个方面，提供一种半导体集成电路，其中输入电路由具有从集电极输出反相输出的双极晶体管和来自发射极的非反相输出的相位分离电路形成。 射极跟随器输出电路由相位分离电路的反相输出驱动。 同时，射极跟随器输出电路的发射极负载由晶体管形成，并且发射极负载晶体管由相分离的非反相输出的上升沿的待充电电容的充电电流导通地临时驱动 电路。 作为本发明的第二方面，逻辑电路由逻辑部分和输出部分组成。 输出部分包括接收由逻辑部分产生的输出信号的射极跟随器输出晶体管和有源下拉晶体管，在其底部接收通过电容元件提供给它的信号。 由有源下拉晶体管接收的信号与提供给所述输出晶体管的基极的输入信号的相位相反。 在有源下拉晶体管的基极和发射极之间设置偏置电路，该偏置电路由其基极接收预定偏置电压的晶体管和发射极电阻构成。 此外，在射极跟随器输出晶体管的连接点和有源下拉晶体管和作为偏置电路的组成部分的晶体管的发射极之间，设置有用于反馈输出信号的电容元件。

    Manufacturing a semiconductor integrated circuit device having on chip logic correction
    50.
    发明授权
    Manufacturing a semiconductor integrated circuit device having on chip logic correction 失效
    制造具有片上逻辑校正的半导体集成电路器件

    公开(公告)号：US5208178A

    公开(公告)日：1993-05-04

    申请号：US738570

    申请日：1991-07-31

    申请人： Mitsuo Usami

    发明人： Mitsuo Usami

    IPC分类号： G01R31/3185 ,  G11C29/00 ,  H01L27/02

    CPC分类号： G01R31/318505 ,  G11C29/006 ,  H01L27/0207

    摘要： The present invention relates to a logic correction for a random logic IC of a high integration density, and more particularly to an on-chip logic correction method wherein the upper surface of a chip is divided into a large number of macrocells, testing of the macrocells is made and each defective macrocell is corrected by replacement. Testing is performed after a primary wiring process that connects semiconductor elements into macrocells but before a secondary wiring process interconnecting the macrocells. After the testing, defective macrocells are replaced, and thereafter the secondary wiring process is performed. Testing is performed using testing pads in each macrocell, connected to the main circuit portion of the macrocell through shift register circuit portions. The macrocells are arranged in a lattice pattern. Wirings formed in the secondary wiring process have a larger cross-sectional area than wirings formed in the primary wiring process.

    摘要翻译： 本发明涉及高积分密度的随机逻辑IC的逻辑校正，更具体地说，涉及一种片上逻辑校正方法，其中芯片的上表面被划分成大量的宏单元，宏单元的测试 并且通过更换来校正每个有缺陷的宏单元。 在将半导体元件连接到宏单元之后但在将宏单元互连的次级布线处理之间的主要布线处理之后执行测试。 在测试之后，更换有缺陷的宏单元，然后进行二次布线处理。 使用每个宏单元中的测试焊盘进行测试，通过移位寄存器电路部分连接到宏单元的主电路部分。 宏单元被布置成格子图案。 在二次布线工艺中形成的布线具有比在主布线工艺中形成的布线更大的横截面面积。