公开(公告)号：US06707098B2

公开(公告)日：2004-03-16

申请号：US09882882

申请日：2001-06-15

申请人： Franz Hofmann ,  Franz Kreupl ,  Richard Johannes Luyken ,  Till Schloesser

发明人： Franz Hofmann ,  Franz Kreupl ,  Richard Johannes Luyken ,  Till Schloesser

IPC分类号： H01L29792

CPC分类号： G11C13/025 ,  B82Y10/00 ,  G11C11/5671 ,  G11C2213/71 ,  G11C2213/77 ,  G11C2213/81 ,  G11C2216/08 ,  H01L51/0048 ,  Y10S438/962 ,  Y10S977/943

摘要： An electronic device has a plurality of electrically conductive first nanowires, a layer system applied on the first nanowires, and also second nanowires applied on the layer system. The first and second nanowires are arranged skew with respect to one another. The layer system is set up in such a way that charge carriers generated by the nanowires can be stored in the layer system.

摘要翻译： 电子器件具有多个导电的第一纳米线，施加在第一纳米线上的层系统，以及施加在层系统上的第二纳米线。 第一和第二纳米线相对于彼此倾斜布置。 层系统的设置使得由纳米线产生的电荷载流子可以存储在层系统中。

公开(公告)号：US5977589A

公开(公告)日：1999-11-02

申请号：US191482

申请日：1998-11-13

申请人： Till Schloesser ,  Wolfgang Krautschneider

发明人： Till Schloesser ,  Wolfgang Krautschneider

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/72

CPC分类号： H01L27/10844 ,  H01L27/108

摘要： A memory cell containing at least three vertical transistors. A first transistor and a second transistor, or a third transistor are arranged over each other with reference to a y-axis proceeding perpendicularly to a surface of a substrate. The second transistor and the third transistor can be arranged at opposite sides of a semiconductor structure, while the first transistor is arranged at both sides. Source/drain regions of the transistors can overlap.

摘要翻译： 一个包含至少三个垂直晶体管的存储单元。 相对于垂直于衬底表面的y轴，第一晶体管和第二晶体管或第三晶体管彼此相互排列。 第二晶体管和第三晶体管可以布置在半导体结构的相对侧，而第一晶体管布置在两侧。 晶体管的源/漏区可以重叠。

公开(公告)号：US20160240661A1

公开(公告)日：2016-08-18

申请号：US15040624

申请日：2016-02-10

申请人： Andreas Meiser ,  Franz Hirler ,  Till Schloesser

发明人： Andreas Meiser ,  Franz Hirler ,  Till Schloesser

IPC分类号： H01L29/78 ,  H01L27/088 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66

CPC分类号： H01L29/7823 ,  H01L21/26586 ,  H01L21/765 ,  H01L21/823437 ,  H01L27/088 ,  H01L29/0661 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66696 ,  H01L29/66704 ,  H01L29/7825

摘要： A semiconductor device formed in a semiconductor substrate having a first main surface comprises a transistor array and a termination region. The transistor array comprises a source region, a drain region, a body region, a drift zone, and a gate electrode at the body region. The gate electrode is configured to control a conductivity of a channel formed in the body region. The gate electrode is disposed in first trenches. The body region and the drift zone are disposed along a first direction between the source region and the drain region, the first direction being parallel to the first main surface. The body region has a shape of a first ridge extending along the first direction. The termination region comprises a termination trench, a portion of the termination trench extending in the first direction, a length of the termination trench being larger than a length of the first trenches, the length being measured along the first direction.

摘要翻译： 形成在具有第一主表面的半导体衬底中的半导体器件包括晶体管阵列和端接区域。 晶体管阵列包括源区域，漏极区域，体区域，漂移区域和在体区域处的栅电极。 栅极被配置为控制在体区中形成的通道的导电性。 栅电极设置在第一沟槽中。 主体区域和漂移区域沿着源极区域和漏极区域之间的第一方向设置，第一方向平行于第一主表面。 身体区域具有沿着第一方向延伸的第一脊的形状。 端接区域包括端接沟槽，端接沟槽的一部分沿第一方向延伸，端接沟槽的长度大于第一沟槽的长度，该长度沿第一方向被测量。

公开(公告)号：US08455960B2

公开(公告)日：2013-06-04

申请号：US13185112

申请日：2011-07-18

申请人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

发明人： Frank Jakubowski ,  Peter Baars ,  Till Schloesser

IPC分类号： H01L29/00

CPC分类号： H01L29/517 ,  H01L21/28088 ,  H01L29/4966 ,  H01L29/7833

摘要： Semiconductor devices are formed with a silicide interface between the work function layer and polycrystalline silicon. Embodiments include forming a high-k/metal gate stack by: forming a high-k dielectric layer on a substrate, forming a work function metal layer on the high-k dielectric layer, forming a silicide on the work function metal layer, and forming a poly Si layer on the silicide. Embodiments include forming the silicide by: forming a reactive metal layer in situ on the work function layer, forming an a-Si layer in situ on the entire upper surface of the reactive metal layer, and annealing concurrently with forming the poly Si Layer.

摘要翻译： 半导体器件在功函数层与多晶硅之间形成硅化物界面。 实施例包括通过以下方式形成高k /金属栅极堆叠：在衬底上形成高k电介质层，在高k电介质层上形成功函数金属层，在功函数金属层上形成硅化物，以及形成 硅化物上的多晶硅层。 实施例包括：通过在功函数层上原位形成反应性金属层，在反应性金属层的整个上表面上原位形成a-Si层，并与形成多晶硅层同时进行退火来形成硅化物。

公开(公告)号：US08222103B1

公开(公告)日：2012-07-17

申请号：US13027739

申请日：2011-02-15

申请人： Peter Baars ,  Till Schloesser

发明人： Peter Baars ,  Till Schloesser

IPC分类号： H01L21/8242 ,  H01L29/94

CPC分类号： H01L27/10852 ,  H01L23/5223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L27/10817 ,  H01L28/92 ,  H01L2924/0002 ,  H01L2924/00

摘要： Generally, the subject matter disclosed herein relates to a semiconductor device with embedded low-k metallization. A method is disclosed that includes forming a plurality of copper metallization layers that are coupled to a plurality of logic devices in a logic area of a semiconductor device and, after forming the plurality of copper metallization layers, forming a plurality of capacitors in a memory array of the semiconductor device. The capacitors are formed using a non-low-k dielectric material (k value greater than 3), while the copper metallization layers are formed in layers of low-k dielectric material (k value less than 3). A semiconductor device is also disclosed which includes a plurality of logic devices, a memory array comprising a plurality of capacitors, a conductive contact plate coupled to the plurality of capacitors, and a plurality of copper metallization layers coupled to the logic devices, wherein the plurality of copper metallization layers are positioned at a level that is below a level of a bottom surface of the contact plate. A material other than a low-k dielectric material is positioned between the plurality of capacitors in the memory array.

摘要翻译： 通常，这里公开的主题涉及具有嵌入式低k金属化的半导体器件。 公开了一种方法，其包括形成耦合到半导体器件的逻辑区域中的多个逻辑器件的多个铜金属化层，并且在形成多个铜金属化层之后，在存储器阵列中形成多个电容器 的半导体器件。 使用非低k电介质材料（k值大于3）形成电容器，而铜金属化层以低k电介质材料（k值小于3）形成。 还公开了一种半导体器件，其包括多个逻辑器件，包括多个电容器的存储器阵列，耦合到多个电容器的导电接触板以及耦合到逻辑器件的多个铜金属化层，其中多个 的铜金属化层被定位在低于接触板的底表面的水平的水平。 除了低k电介质材料之外的材料位于存储器阵列中的多个电容器之间。

公开(公告)号：US07729154B2

公开(公告)日：2010-06-01

申请号：US12028474

申请日：2008-02-08

申请人： Dirk Baumann ,  Dominique Savignac ,  Till Schloesser ,  Helmut Schneider

发明人： Dirk Baumann ,  Dominique Savignac ,  Till Schloesser ,  Helmut Schneider

IPC分类号： G11C5/06

CPC分类号： H01L27/10891

摘要： An integrated circuit with buried control line structures. In one embodiment, the control lines are subdivided into sections, wherein regions free of switching transistors are provided at intervals along the control lines. Connections for feeding the control potentials into the sections of the control lines are provided at least in a subset of the regions free of switching transistors. The isolations lines are connected to one another by an interconnect running transversely with respect to the control lines.

摘要翻译： 具有埋地控制线结构的集成电路。 在一个实施例中，控制线被细分为多个部分，其中不存在开关晶体管的区域沿着控制线间隔设置。 至少在没有开关晶体管的区域的子集中提供用于将控制电位馈送到控制线的部分中的连接。 隔离线通过相对于控制线横向运行的互连而彼此连接。

公开(公告)号：US20100097835A1

公开(公告)日：2010-04-22

申请号：US12252826

申请日：2008-10-16

申请人： Martin Popp ,  Till Schloesser

发明人： Martin Popp ,  Till Schloesser

IPC分类号： G11C5/06 ,  G11C11/24

CPC分类号： G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10882 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated circuit including a memory cell array comprises active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being arranged at a bitline pitch, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, the wordlines being arranged at a wordline pitch, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines, and the bitline pitch is different from the wordline pitch.

摘要翻译： 包括存储单元阵列的集成电路包括有源区线，位线，所述位线被布置成使得单独的位线与多个有源区域线相交以分别形成位线接触，位线布置在位线间距处，字线 被布置为使得单个字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，字线以字线间距排列，其中相邻位线接触，每个 连接到有源区线之一，与不同的位线连接，位线间距与字线间距不同。

公开(公告)号：US20100096669A1

公开(公告)日：2010-04-22

申请号：US12252853

申请日：2008-10-16

申请人： Martin Popp ,  Till Schloesser

发明人： Martin Popp ,  Till Schloesser

IPC分类号： H01L29/76 ,  H01L27/108

CPC分类号： H01L27/10885 ,  H01L27/10882 ,  H01L27/10888 ,  H01L27/10891

摘要： An integrated circuit including a memory cell array comprises transistors being arranged along parallel active area lines, bitlines, the bitlines being arranged so that an individual one intersects a plurality of the active area lines to form bitline-contacts, respectively, the bitlines being formed as wiggled lines, wordlines being arranged so that an individual one of the wordlines intersects a plurality of the active area lines, and an individual one of the wordlines intersects a plurality of the bitlines, wherein neighboring bitline-contacts, each of which is connected to one of the active area lines, are connected with different bitlines.

摘要翻译： 包括存储单元阵列的集成电路包括沿着并行有源区域线，位线布置的晶体管，位线被布置成使得各个相互交叉的多个有源区域线分别形成位线接触，位线形成为 摆动的线条，字线被布置成使得字线中的单个字符与多个有效区域线相交，并且字线中的单个字符与多个位线相交，其中相邻的位线接触，其中每一个连接到一个 的有源面积线与不同的位线连接。

公开(公告)号：US07642572B2

公开(公告)日：2010-01-05

申请号：US11735164

申请日：2007-04-13

申请人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

发明人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

IPC分类号： H01L27/108

CPC分类号： H01L27/10817 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.

摘要翻译： 公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。 一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。 位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。 相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。 以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

公开(公告)号：US07635893B2

公开(公告)日：2009-12-22

申请号：US11128782

申请日：2005-05-13

申请人： Rolf Weis ,  Till Schloesser ,  Ulrike Gruening von Schwerin

发明人： Rolf Weis ,  Till Schloesser ,  Ulrike Gruening von Schwerin

IPC分类号： H01L29/772

CPC分类号： H01L27/10894 ,  H01L27/10808 ,  H01L27/10838 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically insulated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

摘要翻译： 公开了晶体管，存储单元阵列和制造晶体管的方法。 在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是 设置在所述半导体衬底中的栅电极以及沿着所述沟道区设置并与所述沟道区电绝缘的栅极，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括 所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方 基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。