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214 条记录 (耗时 0.036 秒)

    Programmable termination with DC voltage level control
    43.
    发明授权
    Programmable termination with DC voltage level control 有权
    具有直流电压电平控制的可编程终端

    公开(公告)号：US06980022B1

    公开(公告)日：2005-12-27

    申请号：US10946902

    申请日：2004-09-21

    申请人： Sergey Shumarayev ,  Thomas White

    发明人： Sergey Shumarayev ,  Thomas White

    IPC分类号： H04L25/02 ,  H03K19/0175

    CPC分类号： H04L25/0278 ,  H04L25/0272 ,  H04L25/0284 ,  H04L25/0296 ,  H04L25/0298

    摘要： Various embodiments for implementing circuits and systems with highly flexible interface circuitry that is capable of realizing programmable on-chip termination and DC level control. A number of techniques use existing I/O resources to implement programmable on-chip termination and DC level control that enable an integrated circuit to meet a variety of different high speed single-ended and differential I/O standards.

    摘要翻译： 用于实现具有高度灵活的接口电路的电路和系统的各种实施例，其能够实现可编程片上终止和DC电平控制。 许多技术使用现有的I / O资源实现可编程片上终止和DC电平控制，使集成电路能够满足各种不同的高速单端和差分I / O标准。

    Adjustable differential input and output drivers
    45.
    发明授权
    Adjustable differential input and output drivers 有权

    公开(公告)号：US06864704B1

    公开(公告)日：2005-03-08

    申请号：US10669298

    申请日：2003-09-24

    申请人： Wilson Wong ,  Sergey Shumarayev

    发明人： Wilson Wong ,  Sergey Shumarayev

    IPC分类号： H03K19/0185 ,  H04L25/02 ,  H03K17/16

    CPC分类号： H04L25/0276 ,  H03K19/018564

    摘要： Systems and methods are provided using common-mode-voltage bias circuitry to make common-mode-voltage adjustments to differential driver circuitry in integrated circuit differential communications links. Adjustable bias circuitry may be controlled using static and dynamic control signals. Dynamic control signals can be produced by core logic on a programmable logic device or other integrated circuit. Static control signals can be produced by programmable elements. Bias circuit adjustments made at one end of a differential link can be used to improve performance at either end of the link or can be used to improve power consumption or to balance power and performance considerations. The same integrated circuit design can be used in both AC-coupled and DC-coupled environments. The bias circuitry can be formed from an adjustable current source and adjustable resistor. The current source and adjustable resistors can be controlled by the same control signals.

    Interconnection resources for programmable logic integrated circuit devices
    46.
    发明授权
    Interconnection resources for programmable logic integrated circuit devices 有权
    可编程逻辑集成电路器件的互连资源

    公开(公告)号：US06366120B1

    公开(公告)日：2002-04-02

    申请号：US09517146

    申请日：2000-03-02

    申请人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    发明人： James Schleicher ,  James Park ,  Sergey Shumarayev ,  Bruce Pedersen ,  Tony Ngai ,  Wei-Jen Huang ,  Victor Maruri ,  Rakesh Patel

    IPC分类号： H03K190177

    CPC分类号： G06F7/506 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17744 ,  H03K19/17792

    摘要： A programmable logic device has many regions of programmable logic, together with relatively general-purpose, programmable, interconnection resources that can be used to make interconnections between virtually any of the logic regions. In addition, various types of more local interconnection resources are associated with each logic region for facilitating the making of interconnections between adjacent or nearby logic regions without the need to use the general-purpose interconnection resources for those interconnections. The local interconnection resources support flexible clustering of logic regions via relatively direct and therefore high-speed interconnections, preferably in both horizontal and vertical directions in the typically two-dimensional array of logic regions. The logic region clustering options provided by the local interconnection resources are preferably boundary-less or substantially boundary-less within the array of logic regions.

    摘要翻译： 可编程逻辑器件具有许多可编程逻辑区域，以及可用于在几乎任何逻辑区域之间进行互连的相对通用的，可编程的互连资源。 此外，各种类型的更多本地互连资源与每个逻辑区域相关联，以便于在相邻或附近的逻辑区域之间建立互连，而不需要使用这些互连的通用互连资源。 本地互连资源通过相对直接的和因此的高速互连来支持逻辑区域的灵活聚集，优选地在逻辑区域的典型二维阵列中的水平和垂直方向。 由本地互连资源提供的逻辑区域聚类选项优选地在逻辑区域阵列内是无边界的或基本无边界的。

    Integrated circuits with configurable inductors
    48.
    发明授权
    Integrated circuits with configurable inductors 有权
    具有可配置电感器的集成电路

    公开(公告)号：US08836443B2

    公开(公告)日：2014-09-16

    申请号：US13617347

    申请日：2012-09-14

    申请人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

    发明人： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Ali Atesoglu ,  Sharat Babu Ippili

    IPC分类号： H01L23/66 ,  H03B5/08 ,  H03C3/22 ,  H01F27/29 ,  H03B5/12 ,  H01F27/28 ,  H01F21/12

    CPC分类号： H03B5/1212 ,  H01F2021/125 ,  H01F2027/2809 ,  H01L2924/0002 ,  H03B5/1243 ,  H03B5/1268 ,  H01L2924/00

    摘要： Integrated circuits with phase-locked loops are provided. Phase-locked loops may include an oscillator, a phase-frequency detector, a charge pump, a loop filter, a voltage-controlled oscillator, and a programmable divider. The voltage-controlled oscillator may include multiple inductors, an oscillator circuit, and a buffer circuit. A selected one of the multiple inductors may be actively connected to the oscillator circuit. The voltage-controlled oscillators may have multiple oscillator circuits. Each oscillator circuit may be connected to a respective inductor, may include a varactor, and may be powered by a respective voltage regulator. Each oscillator circuit may be coupled to a respective input transistor pair in the buffer circuit through associated coupling capacitors. A selected one of the oscillator circuits may be turned on during normal operation by supplying a high voltage to the selected one of the oscillator circuit and by supply a ground voltage to the remaining oscillator circuits.

    摘要翻译： 提供具有锁相环的集成电路。 锁相环可以包括振荡器，相位频率检测器，电荷泵，环路滤波器，压控振荡器和可编程分频器。 压控振荡器可以包括多个电感器，振荡器电路和缓冲电路。 多个电感器中选择的一个可以主动地连接到振荡器电路。 压控振荡器可以具有多个振荡器电路。 每个振荡器电路可以连接到相应的电感器，可以包括变容二极管，并且可以由相应的电压调节器供电。 每个振荡器电路可以通过相关联的耦合电容器耦合到缓冲电路中的相应输入晶体管对。 所选择的一个振荡器电路可以在正常操作期间通过向所选振荡器电路中的一个提供高电压并且向剩余的振荡器电路提供接地电压而导通。

    Multi-purpose phase-locked loop for low cost transceiver
    49.
    发明授权
    Multi-purpose phase-locked loop for low cost transceiver 有权
    用于低成本收发器的多功能锁相环

    公开(公告)号：US08619931B1

    公开(公告)日：2013-12-31

    申请号：US12622152

    申请日：2009-11-19

    申请人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

    发明人： Tien Duc Pham ,  Sergey Shumarayev ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Vinh Van Ho ,  Leon Zheng

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0337 ,  H04L7/002

    摘要： Integrated circuits having transceivers capable of high-speed (e.g., 1 Gbps) operation without dedicated phase-locked loop circuitry are provided. One such integrated circuit device may include one or more transceivers capable of transmitting and receiving serial signals of approximately 1 Gbps or greater, and a multi-purpose phase-locked loop capable of providing a multi-phase clock signal to the one or more transceivers.

    摘要翻译： 提供了具有能够在没有专用锁相环电路的情况下能够进行高速（例如，1Gbps）操作的收发器的集成电路。 一个这样的集成电路设备可以包括能够发送和接收大约1Gbps或更大的串行信号的一个或多个收发器，以及能够向一个或多个收发器提供多相时钟信号的多用途锁相环。

    Apparatus and methods for low-jitter transceiver clocking
    50.
    发明授权
    Apparatus and methods for low-jitter transceiver clocking 有权
    低抖动收发器时钟的装置和方法

    公开(公告)号：US08406258B1

    公开(公告)日：2013-03-26

    申请号：US12752984

    申请日：2010-04-01

    申请人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    发明人： Wilson Wong ,  Tim Tri Hoang ,  Thungoc M. Tran ,  Sergey Shumarayev ,  Allen Chan

    IPC分类号： H04J3/06

    CPC分类号： H03M9/00 ,  H03K19/1776 ,  H04J3/047 ,  H04J3/0685

    摘要： One embodiment relates to an integrated circuit which includes multiple communication channels, a clock multiplexer in each channel, two low-jitter clock generator circuits, and clock distribution circuitry. Each channel includes circuitry arranged to communicate a serial data stream using a reference clock signal, and the clock multiplexer in each channel is configured to select the reference clock signal from a plurality of input clock signals. The first low-jitter clock generator circuit is arranged to generate a first clock signal using a first inductor-capacitor-based oscillator circuit, and the second low-jitter clock generator circuit is arranged to generate a second clock signal using a second inductor-capacitor-based oscillator circuit The first and second inductor-capacitor-based oscillator circuits have different tuning ranges. The clock distribution circuitry is arranged to input the first and second low-jitter clock signals to each said clock multiplexer. Other embodiments and features are also disclosed.

    摘要翻译： 一个实施例涉及一种集成电路，其包括多个通信信道，每个信道中的时钟多路复用器，两个低抖动时钟发生器电路和时钟分配电路。 每个通道包括被布置为使用参考时钟信号传送串行数据流的电路，并且每个通道中的时钟复用器被配置为从多个输入时钟信号中选择参考时钟信号。 第一低抖动时钟发生器电路被布置为使用第一基于电感器 - 电容器的振荡器电路产生第一时钟信号，并且第二低抖动时钟发生器电路被布置为使用第二电感器电容器产生第二时钟信号 基振荡电路基于第一和第二电感电容器的振荡电路具有不同的调谐范围。 时钟分配电路被布置为将第一和第二低抖动时钟信号输入到每个所述时钟多路复用器。 还公开了其它实施例和特征。