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公开(公告)号：US09093565B2
公开(公告)日：2015-07-28
申请号：US13941555
申请日：2013-07-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Tzu Wang , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L21/70 , H01L29/861 , H01L21/76 , H01L27/02
CPC classification number: H01L27/0255 , H01L21/22 , H01L21/265 , H01L21/30604 , H01L21/76 , H01L21/76224 , H01L27/0629 , H01L29/0642 , H01L29/0649 , H01L29/0657 , H01L29/0692 , H01L29/1606 , H01L29/2003 , H01L29/6609 , H01L29/66136 , H01L29/785 , H01L29/861
Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.
Abstract translation: 在本发明中提供了一种鳍式二极管结构及其制造方法，其结构包括：衬底，在衬底中形成的掺杂阱，多个第一导电类型的鳍和多个第二导电类型的鳍从 掺杂阱以及在第一导电类型的散热片，第二导电类型的散热片，浅沟槽隔离和掺杂阱之间的基板中全局形成的第一导电类型的掺杂区域，并与第一掺杂型的鳍片连接，以及 第二掺杂型散热片。
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公开(公告)号：US08981521B1
公开(公告)日：2015-03-17
申请号：US13974939
申请日：2013-08-23
Applicant: United Microelectronics Corp.
Inventor： Chang-Tzu Wang , Pei-Shan Tseng , Tien-Hao Tang
IPC: H01L29/735 , H01L29/73 , H01L29/66
CPC classification number: H01L29/735 , H01L27/0259 , H01L29/0821 , H01L29/6625 , H01L29/861
Abstract: Provided is a lateral BJT including a substrate, a well region, an area, at least one lightly doped region, a first doped region, and a second doped region. The substrate is of a first conductivity type. The well region is of a second conductivity type and is in the substrate. The area is in the well region. The at least one lightly doped region is in the well region below the area. The first doped region and the second doped region are of the first conductivity type and are in the well region on both sides of the area. The first doped region is connected to a cathode. The second doped region is connected to an anode, wherein the doping concentration of the at least one lightly doped region is lower than that of each of the first doped region, the second doped region, and the well region.
Abstract translation: 提供了包括衬底，阱区，区域，至少一个轻掺杂区域，第一掺杂区域和第二掺杂区域的横向BJT。 衬底是第一导电类型。 阱区是第二导电类型并且在衬底中。 该地区在该地区。 至少一个轻掺杂区域位于该区域下方的阱区域中。 第一掺杂区域和第二掺杂区域是第一导电类型并且在该区域两侧的阱区域中。 第一掺杂区域连接到阴极。 第二掺杂区域连接到阳极，其中至少一个轻掺杂区域的掺杂浓度低于第一掺杂区域，第二掺杂区域和阱区域中的每一个的掺杂浓度。
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公开(公告)号：US20150014809A1
公开(公告)日：2015-01-15
申请号：US13941555
申请日：2013-07-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chang-Tzu Wang , Ping-Chen Chang , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L29/861 , H01L21/76
CPC classification number: H01L27/0255 , H01L21/22 , H01L21/265 , H01L21/30604 , H01L21/76 , H01L21/76224 , H01L27/0629 , H01L29/0642 , H01L29/0649 , H01L29/0657 , H01L29/0692 , H01L29/1606 , H01L29/2003 , H01L29/6609 , H01L29/66136 , H01L29/785 , H01L29/861
Abstract: A fin diode structure and method of manufacturing the same is provided in present invention, which the structure includes a substrate, a doped well formed in the substrate, a plurality of fins of first conductivity type and a plurality of fins of second conductivity type protruding from the doped well, and a doped region of first conductivity type formed globally in the substrate between the fins of first conductivity type, the fins of second conductivity type, the shallow trench isolation and the doped well and connecting with the fins of first doped type and the fins of second doped type.
Abstract translation: 在本发明中提供了一种鳍式二极管结构及其制造方法，其结构包括：衬底，在衬底中形成的掺杂阱，多个第一导电类型的鳍和多个第二导电类型的鳍从 掺杂阱以及在第一导电类型的散热片，第二导电类型的散热片，浅沟槽隔离和掺杂阱之间的基板中全局形成的第一导电类型的掺杂区域，并与第一掺杂型的鳍片连接，以及 第二掺杂型散热片。
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44.发明授权公开(公告)号：US08896024B1
公开(公告)日：2014-11-25
申请号：US13940081
申请日：2013-07-11
Applicant: United Microelectronics Corp.
Inventor： Yi-Chun Chen , Li-Cih Wang , Lu-An Chen , Tien-Hao Tang
CPC classification number: H01L27/0262 , H01L29/7412 , H01L29/7436 , H01L29/87
Abstract: Provided is an electrostatic discharge (ESD) protection structure including a first and a second well region adjacent to each other, a first and a second doped region disposed in the first well region, a fourth and a fifth doped region disposed in the second well region, and a third doped region disposed in the first region and extending into the second well region. The second doped region is disposed between the first and the third doped regions, forming a diode with the first doped region, forming, together with the first well region and the second well region, a first bipolar junction transistor (BJT) electrically connecting to the diode, and having no contact window disposed thereon. The fourth doped region is disposed between the third and the fifth doped regions, forming a second BJT with the second well region and the first well region.
Abstract translation: 提供一种静电放电（ESD）保护结构，其包括彼此相邻的第一和第二阱区，设置在第一阱区中的第一和第二掺杂区，设置在第二阱区中的第四和第五掺杂区 以及设置在第一区域中并延伸到第二阱区域中的第三掺杂区域。 第二掺杂区域设置在第一和第三掺杂区域之间，形成具有第一掺杂区域的二极管，与第一阱区域和第二阱区域一起形成电连接到第一掺杂区域的第一双极结型晶体管（BJT） 二极管，并且没有布置在其上的接触窗口。 第四掺杂区域设置在第三和第五掺杂区域之间，与第二阱区域和第一阱区域形成第二BJT。
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公开(公告)号：US20250120185A1
公开(公告)日：2025-04-10
申请号：US18981624
申请日：2024-12-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hou-Jen Chiu , Mei-Ling Chao , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/02
Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.
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Patent Agency Ranking
公开(公告)号：US20240162218A1
公开(公告)日：2024-05-16
申请号：US18164622
申请日：2023-02-06
Applicant: United Microelectronics Corp.
Inventor： Chih Hsiang Chang , Mei-Ling Chao , Yin-Chia Tsai , Tien-Hao Tang , Kuan-Cheng Su
CPC classification number: H01L27/0255 , H01L21/84 , H01L27/0259 , H01L27/0266 , H01L27/0292 , H01L27/0296
Abstract: An electrostatic discharge device including a gate structure, a plurality of first doped regions, and a plurality of second doped regions. The gate structure is disposed on a substrate. The gate structure includes a body part and a plurality of extension parts. The extension parts are connected with the body part, and an extension direction of the body part is different from an extension direction of the extension parts. The first doped regions are located in the substrate between the extension parts. The second doped regions are located in the substrate at two outer sides of the extension parts. The first doped regions and the second doped regions have different conductivity types.
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公开(公告)号：US20230326919A1
公开(公告)日：2023-10-12
申请号：US17742392
申请日：2022-05-11
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Hou-Jen Chiu , Mei-Ling Chao , Tien-Hao Tang , Kuan-Cheng Su
IPC: H01L27/02
CPC classification number: H01L27/0259
Abstract: An electrostatic discharge protection structure includes a semiconductor substrate, a gate structure disposed on the semiconductor substrate, a first well region of a first conductivity type disposed in the semiconductor substrate, a first doped region of the first conductivity type, a second doped region of a second conductivity type, a third doped region of the first conductivity type, and a fourth doped region of the second conductivity type. The first and second doped regions are disposed in the first well region and connected with each other. The second doped region is an emitter of a first bipolar junction transistor. The third and fourth doped regions are disposed in the semiconductor substrate and connected with each other. The third and second doped regions are located at two opposite sides of the gate structure in a first horizontal direction. The third doped region is an emitter of a second bipolar junction transistor.
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公开(公告)号：US10903205B2
公开(公告)日：2021-01-26
申请号：US16394967
申请日：2019-04-25
Applicant: United Microelectronics Corp.
Inventor： Ting-Yao Lin , Chun Chiang , Ping-Chen Chang , Tien-Hao Tang
Abstract: A semiconductor device of ESD protection includes a first P-type well in a substrate to receive a protected terminal and a first N-type well abutting the first P-type well in the substrate. A second P-type well abutting the first N-type well is in the substrate. A second N-type well abutting the second P-type well is in the substrate. A detective circuit device is formed on a surface of the substrate, having an input terminal to receive the protected terminal and an output terminal to provide a trigger voltage to the first N-type well. A first route structure is in the substrate, on a sidewall and a bottom of the first P-type well to connect to a bottom of the first N-type well. A second route structure is in the substrate, on sidewall and bottom of the second N-type well, to connect to a bottom of the second P-type well.
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公开(公告)号：US20200235088A1
公开(公告)日：2020-07-23
申请号：US16844986
申请日：2020-04-09
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chung-Yu Huang , Kuan-Cheng Su , Tien-Hao Tang , Ping-Jui Chen , Po-Ya Lai
IPC: H01L27/02 , H01L27/088 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/423
Abstract: An ESD protection semiconductor device includes a substrate. A gate set disposed on the substrate. A plurality of source fins and a plurality of drain fins having a first conductivity type are disposed in the substrate respectively at two sides of the gate set. A first doped fin is disposed in the substrate and positioned in between the source fins and spaced apart from the source fins. The first doped fin comprises a second conductivity type that is complementary to the first conductivity type. A second doped fin is formed in one of the drain fins and isolated from the one of the drain fins by an isolation structure. The second doped fin is electrically connected to the first doped fin.
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50.发明授权公开(公告)号：US10522530B2
公开(公告)日：2019-12-31
申请号：US15927107
申请日：2018-03-21
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chun Chiang , Ying-Wei Tseng , Ping-Chen Chang , Tien-Hao Tang
Abstract: An electrostatic discharge (ESD) shielding semiconductor device and an ESD testing method thereof, the ESD shielding semiconductor device includes an integrated circuit, a seal ring and a conductive layer. The integrated circuit is disposed on a die, and the integrated circuit has a first region and a second region. The seal ring is disposed on the die to surround the integrated circuit. The conductive layer at least covers the first region, and which is electrically connected to the seal ring.
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