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公开(公告)号：US4438158A
公开(公告)日：1984-03-20
申请号：US437046
申请日：1982-10-27
IPC分类号： H01C17/065 , B05D5/12 , H01C7/00
CPC分类号： H01C17/06533
摘要： An electrical resistor family based on oxides of tungsten and/or molybdenum is prepared by combining a polymeric binder with such oxides in an appropriate amount to realize the desired bulk properties. The resistance of the composite can be varied by varying the metal content of the oxides and/or by appropriate combination of the various oxides. Inert fillers are not required and the bulk properties are more stable.
摘要翻译： 基于钨和/或钼的氧化物的电阻器系列通过将聚合物粘合剂与这种氧化物合适的量合并来实现所需的体积特性来制备。 可以通过改变氧化物的金属含量和/或通过各种氧化物的适当组合来改变复合材料的电阻。 不需要惰性填料，体积性能更稳定。
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42.发明授权Electrical conductor interconnect providing solderable connections to hard-to-contact substrates, such as liquid crystal cells 失效电导体互连件提供与硬接触衬底（例如液晶单元）的可焊接连接
公开(公告)号：US4362903A
公开(公告)日：1982-12-07
申请号：US220331
申请日：1980-12-29
CPC分类号： H05K3/246 , H05K1/095 , H05K2201/0326 , H05K2201/0347 , H05K3/244
摘要： An electrical conductor interconnect is disclosed which permits hard-to-contact substrates, such as the glass substrate in liquid crystal display cells, to be connected to electrical apparatus by conventional soldering techniques. The interconnect conductor involves the use of a polymer loaded with both a conducting powder and a non-noble metal powder whose top surface is coated with a contiguous layer of an adherent solderable metal by an augmentation replacement reaction.
摘要翻译： 公开了一种电导体互连件，其允许诸如液晶显示单元中的玻璃基板的难接触的基板通过常规的焊接技术连接到电气设备。 互连导体包括使用负载有导电粉末和非贵金属粉末的聚合物，其顶表面通过增加置换反应被粘附的可焊接金属的邻接层涂覆。
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公开(公告)号：US4345236A
公开(公告)日：1982-08-17
申请号：US220344
申请日：1980-12-29
CPC分类号： H01C10/305 , H01C10/38 , Y10T29/49082
摘要： An abrasion-resistant screen-printed potentiometer includes top and bottom resistive layers screen-printed on a substrate. The resistivity of the top layer is substantially greater than the resistivity of the bottom layer. A slide arm is in pressure contact with the top layer and is slidably movable thereacross.
摘要翻译： 耐磨丝网印刷电位器包括丝网印刷在基材上的顶部和底部电阻层。 顶层的电阻率基本上大于底层的电阻率。 滑动臂与顶层压力接触并且可滑动地在其上移动。
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公开(公告)号：US4301509A
公开(公告)日：1981-11-17
申请号：US93685
申请日：1979-11-13
申请人： Michael A. Haase , Edward B. Miller , Charles W. Eichelberger , Scott E. Cutler , Robert J. Wojnarowski
发明人： Michael A. Haase , Edward B. Miller , Charles W. Eichelberger , Scott E. Cutler , Robert J. Wojnarowski
摘要： Meat or poultry is cooked automatically in a thermal oven to a desired degree of doneness by a chosen time. The temperature of the meat or poultry is monitored, and linear extrapolations are made therefrom. These extrapolations are compared to the course the cooking should follow, and the oven temperature is automatically varied to correct deviations from the ideal course.
摘要翻译： 肉或家禽在热烘箱中自动烹饪至所需时间的期望程度。 监测肉类或家禽的温度，并由此进行线性外推。 将这些外推与烹饪应遵循的过程进行比较，并且烘箱温度自动变化，以纠正与理想过程的偏差。
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公开(公告)号：US4268779A
公开(公告)日：1981-05-19
申请号：US66286
申请日：1979-08-13
CPC分类号： H05B6/681
摘要： A circuit for controlling power consumption of a load, by controlling the flow of current thereto, utilizes at least one parallel combination of non-linear resistance elements, such as a varistor and the like, and a gateable semiconductor switching device, such as a triac and the like, to substantially reduce or prevent current flow when the semiconductor switching device is gated to an "off" condition and to enable normal current flow to a load when the semiconductor switching device is gated to an "on" condition. Embodiments of the power circuits for control of magnetron power, in a microwave oven, are illustrated.
摘要翻译： 用于通过控制电流的流量来控制负载的功耗的电路利用非线性电阻元件（例如变阻器等）的至少一个并联组合，以及可选择的半导体开关器件，例如三端双向可控硅开关元件 当半导体开关器件选通到“关闭”状态并且当半导体开关器件选通到“导通”状态时能够使负载正常流动，从而大大减少或防止电流流动。 示出了在微波炉中控制磁控管功率的电源电路的实施例。
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46.发明授权Flexible high density interconnect structure and flexibly interconnected system 失效灵活的高密度互连结构和灵活互连的系统
公开(公告)号：US5452182A
公开(公告)日：1995-09-19
申请号：US865786
申请日：1992-04-07
IPC分类号： H01L23/52 , H01L21/00 , H01L21/68 , H01L23/538 , H01L25/04 , H01L25/065 , H01L25/18 , H05K1/02 , H05K1/05 , H05K1/14 , H05K1/18 , H05K3/00 , H05K1/11
CPC分类号： H05K1/189 , H01L21/67144 , H01L21/6835 , H01L23/5387 , H01L23/5389 , H01L24/24 , H01L24/82 , H01L25/0655 , H01L2221/68313 , H01L2224/24227 , H01L2224/7665 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H05K1/05 , H05K2201/051 , H05K2201/09745 , H05K2201/2009 , H05K2203/0264 , H05K3/0058
摘要： A flexible high density interconnect structure is provided by extending the high density interconnect structure beyond the solid substrate containing the chips interconnected thereby. During fabrication, the flexible portion of the high density interconnect structure is supported by a temporary interconnect support to facilitate fabrication of the structure in accordance with existing fabrication techniques. Subsequently, that temporary support structure may be removed or may remain in place if it sufficiently flexible to impart the desired degree of flexibility to that portion of the high density interconnect structure. Methods of fabrication are also disclosed.
摘要翻译： 通过将高密度互连结构延伸超过含有由此相互连接的芯片的固体基板而提供灵活的高密度互连结构。 在制造期间，高密度互连结构的柔性部分由临时互连支撑支撑，以便于根据现有制造技术制造结构。 随后，如果临时支撑结构足够柔软以赋予该高密度互连结构部分所需的柔性程度，那么该临时支撑结构可被移除或保持在适当位置。 还公开了制造方法。
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公开(公告)号：US5331203A
公开(公告)日：1994-07-19
申请号：US141460
申请日：1993-10-25
IPC分类号： H01L23/538 , H01L23/02 , H01L23/12
CPC分类号： H01L24/82 , H01L23/5389 , H01L24/24 , H01L2224/2402 , H01L2224/24227 , H01L2224/82039 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01027 , H01L2924/01032 , H01L2924/01033 , H01L2924/01039 , H01L2924/01052 , H01L2924/01058 , H01L2924/01068 , H01L2924/01072 , H01L2924/01074 , H01L2924/01075 , H01L2924/01082 , H01L2924/10329 , H01L2924/12033 , H01L2924/12042 , H01L2924/14 , H01L2924/1423 , H01L2924/15151 , H01L2924/15153 , H01L2924/15165 , H01L2924/15787 , H01L2924/19042 , H01L2924/30107 , H01L2924/3011
摘要： A high density interconnect structure is rendered suitable for the packaging of overlay sensitive chips by providing a cavity in the high density interconnect structure which spaces the sensitive surface of such chips from the overlying high density interconnect structure in a manner which prevents undesired interactions between the dielectric of the high density interconnect structure and the chip.
摘要翻译： 通过在高密度互连结构中提供空腔使得高密度互连结构适合于覆盖敏感芯片的封装，其将这种芯片的敏感表面与上覆的高密度互连结构隔离，以防止电介质之间的不期望的相互作用 的高密度互连结构和芯片。
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公开(公告)号：US5258647A
公开(公告)日：1993-11-02
申请号：US936712
申请日：1992-08-26
IPC分类号： H01L23/00 , H01L23/498 , H01L23/538 , H01L29/78
CPC分类号： H01L23/562 , H01L23/4985 , H01L23/5389 , H01L24/24 , H01L24/75 , H01L24/82 , H01L2224/2402 , H01L2224/24225 , H01L2224/24227 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2224/73267 , H01L2224/75315 , H01L24/48 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/16195 , H01L2924/19041
摘要： A high acceleration object includes an electronic system which is operable at accelerations in excess of 20,000 g. Connections between integrated circuit chips and other portions of the electronic system are provided by metallization patterns disposed on polymer dielectric layers which are self-supporting across gaps between components. A high density interconnect structure is disposed within the cavity of a hermetically sealed package.
摘要翻译： 高加速度对象包括可在超过20,000g的加速度下操作的电子系统。 集成电路芯片和电子系统的其它部分之间的连接由设置在聚合物电介质层上的金属化图案提供，其跨组件之间的间隙自支撑。 高密度互连结构设置在密封封装的空腔内。
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49.发明授权Integrated circuit packaging configuration for rapid customized design and unique test capability 失效集成电路封装配置，快速定制设计和独特的测试能力
公开(公告)号：US5214655A
公开(公告)日：1993-05-25
申请号：US784094
申请日：1991-10-28
IPC分类号： G01R31/3185 , H01L23/538
CPC分类号： H01L23/5382 , G01R31/318505 , H01L2924/0002 , H01L2924/3011
摘要： A packaged electronics system, having respective portions each with respective input and output ports, and having interconnection busses between certain of these ports, is tested as follows. Each input port has a set of first transmission gates associated therewith for selectively disconnecting it during testing from the end of each interconnection bus connected bit during normal operation. Each input port has a second set of transmission gates associated therewith for selectively applying test vectors thereto during testing as provided in parallel form from a serially loaded shift register. Each output port connects to the input connections of a respective set of tristate drivers for selectively applying its output signals at relatively low source impedance to at least one interconnection bus connected from the output connections of that set of tristate drivers. A shift register converts the signals appearing in parallel at least one end of each interconnection bus to a concatenation of test results in serial form.
摘要翻译： 具有相应部分的封装电子系统各自具有相应的输入和输出端口，并且在这些端口中的某些端口之间具有互连总线，如下进行测试。 每个输入端口具有与其相关联的一组第一传输门，用于在正常操作期间从每个互连总线连接的位的端部进行测试时选择性地断开它。 每个输入端口具有与之相关联的第二组传输门，用于在测试期间选择性地将测试向量应用于串行装载的移位寄存器的并行形式。 每个输出端口连接到相应组的三态驱动器的输入连接，用于选择性地将其输出信号以相对低的源阻抗施加到从该组三态驱动器的输出连接连接的至少一个互连总线。 移位寄存器将并联出现的每个互连总线的至少一端的信号以串行形式连接到测试结果。
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公开(公告)号：US5200810A
公开(公告)日：1993-04-06
申请号：US504749
申请日：1990-04-05
IPC分类号： H01L23/52 , H01L23/538 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18 , H01L27/00 , H05K1/02 , H05K1/14 , H05K1/18
CPC分类号： H01L23/5389 , H01L2224/05554 , H01L2224/16225 , H01L2224/451 , H01L2224/48091 , H01L2224/48227 , H01L2224/49175 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01039 , H01L2924/01078 , H01L2924/12042 , H01L2924/14 , H01L2924/19041 , H05K1/181 , H05K1/182 , Y10S257/93
摘要： The functionality, versatility and connection and packing density of a high density interconnect structure is enhanced by mounting one or more components on top of the high density interconnect structure for connection to conductors of the high density interconnect structure and the chips embedded within the high density interconnect structure. Both active and passive components may be mounted in this manner, as may components which would be adversely affected by high density interconnect structure fabrication temperatures or by the presence of the high density interconnect structure dielectric.
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