中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

58 records (took 0.019 seconds)

    Package integration for laterally mounted IC dies with dissimilar solder interconnects
    43.
    发明授权
    Package integration for laterally mounted IC dies with dissimilar solder interconnects 有权

    公开(公告)号：US11373989B1

    公开(公告)日：2022-06-28

    申请号：US17006745

    申请日：2020-08-28

    Applicant: XILINX, INC.

    Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam

    IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

    Abstract: A chip package assembly and method of fabricating the same are described herein. The chip package assembly generally includes at least one integrated circuit (IC) die that has had the original solder interconnects at least partially replaced to enhance the reliability of a redistribution layer disposed between the IC die and the substrate. In the resulting chip package assembly, at least one IC die includes first and second pillars extending from exposed contact pads through a first mold compound. The second pillars are fabricated from a material that has a composition different than that of the first pillars. A redistribution layer is formed on the first and second pillars. The solder interconnects mechanically couple the redistribution layer to landing pads of a substrate. The solder interconnects also electrically couple circuitry of the substrate to the circuitry of the IC die through the redistribution layer and first and second pillars.

    Three-dimensional thermal management apparatuses for electronic devices
    45.
    发明授权
    Three-dimensional thermal management apparatuses for electronic devices 有权

    公开(公告)号：US11328976B1

    公开(公告)日：2022-05-10

    申请号：US16808023

    申请日：2020-03-03

    Applicant: XILINX, INC.

    Inventor： Gamal Refai-Ahmed ,  Chi-Yi Chao ,  Suresh Ramalingam ,  Hoa Lap Do ,  Anthony Torza ,  Brian D. Philofsky

    IPC: H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L23/42

    Abstract: Some examples described herein provide for three-dimensional (3D) thermal management apparatuses for thermal energy dissipation of thermal energy generated by an electronic device. In an example, an apparatus includes a thermal management apparatus that includes a primary base, a passive two-phase flow thermal carrier, and fins. The thermal carrier has a carrier base and one or more sidewalls extending from the carrier base. The carrier base and the one or more sidewalls are a single integral piece. The primary base is attached to the thermal carrier. The carrier base has an exterior surface that at least a portion of which defines a die contact region. The thermal carrier has an internal volume aligned with the die contact region. A fluid is disposed in the internal volume. The fins are attached to and extend from the one or more sidewalls of the thermal carrier.

    STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT
    46.
    发明申请
    STACKED SILICON PACKAGE ASSEMBLY HAVING VERTICAL THERMAL MANAGEMENT 有权

    公开(公告)号：US20210193620A1

    公开(公告)日：2021-06-24

    申请号：US16718868

    申请日：2019-12-18

    Applicant: Xilinx, Inc.

    Inventor： Gamal Refai-Ahmed ,  Suresh Ramalingam ,  Jaspreet Singh Gandhi ,  Cheang-Whang Chang

    IPC: H01L25/065 ,  H01L23/04 ,  H01L23/31 ,  H01L23/367

    Abstract: A chip package assembly and method for fabricating the same are provided which utilize a plurality of electrically floating extra-die heat transfer posts for improved thermal management. In one example, a chip package assembly is provided that includes a substrate, a first integrated circuit (IC) die, and a first plurality of electrically floating extra-die conductive posts. The substrate has a first surface and an opposing second surface. The first integrated circuit (IC) die has a first surface and an opposing second surface. The second surface of the first IC die is mounted to the first surface of the substrate. The first plurality of electrically floating extra-die conductive posts extend from the first surface of the first IC die to provide a heat transfer path away from the first IC die.

    Multi-chip silicon substrate-less chip packaging
    47.
    发明授权
    Multi-chip silicon substrate-less chip packaging 有权

    公开(公告)号：US10468351B2

    公开(公告)日：2019-11-05

    申请号：US14469500

    申请日：2014-08-26

    Applicant: Xilinx, Inc.

    Inventor： Woon-Seong Kwon ,  Suresh Ramalingam

    IPC: H01L23/538 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L25/07 ,  H01L23/16 ,  H01L21/683 ,  H01L23/498 ,  H01L23/31

    Abstract: Examples generally provide a stacked silicon interconnect product and method of manufacture. The stacked silicon interconnect product includes a silicon substrate-less interposer comprising a plurality of metallization layers, wherein at least one metallization layer includes a plurality of metal segments separated by dielectric material. The stacked silicon interconnect product also includes a first die coupled to a first side of the silicon substrate-less interposer via a first plurality of microbumps. The stacked silicon interconnect product further includes a second die coupled to a second side of the silicon substrate-less interposer via a second plurality of microbumps, the second die communicatively coupled to the first die through a metallization layer of the plurality of metallization layers.

    METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION
    50.
    发明申请
    METHODS OF INTERCONNECT FOR HIGH DENSITY 2.5D AND 3D INTEGRATION 审中-公开

    公开(公告)号：US20180286826A1

    公开(公告)日：2018-10-04

    申请号：US15473294

    申请日：2017-03-29

    Applicant: Xilinx, Inc.

    Inventor： Jaspreet Singh Gandhi ,  Suresh Ramalingam ,  Henley Liu

    IPC: H01L23/00 ,  H01L25/065 ,  H01L23/498

    Abstract: Methods and apparatus are described for enabling copper-to-copper (Cu—Cu) bonding at reduced temperatures (e.g., at most 200° C.) by significantly reducing Cu oxide formation. These techniques provide for faster cycle time and entail no extraordinary measures (e.g., forming gas). Such techniques may also enable longer queue (Q) or staging times. One example semiconductor structure generally includes a semiconductor layer, an adhesion layer disposed above the semiconductor layer, an anodic metal layer disposed above the adhesion layer, and a cathodic metal layer disposed above the anodic metal layer. An oxidation potential of the anodic metal layer may be greater than an oxidation potential of the cathodic metal layer. Such a semiconductor structure may be utilized in fabricating IC packages implementing 2.5D or 3D integration.

Patent Agency Ranking