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    Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure
    41.
    发明授权
    Heterojunction bipolar transistor with reduced sub-collector length, method of manufacture and design structure 有权
    具有减小的集电极长度的异质结双极晶体管，制造方法和设计结构

    公开(公告)号：US09059138B2

    公开(公告)日：2015-06-16

    申请号：US13358180

    申请日：2012-01-25

    申请人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    发明人： Renata Camillo-Castillo ,  Zhong-Xiang He ,  Jeffrey B. Johnson ,  Qizhi Liu ,  Xuefeng Liu

    IPC分类号： H01L29/737 ,  G06F17/50 ,  H01L21/331 ,  H01L29/417 ,  H01L29/66 ,  H01L29/10

    CPC分类号： H01L29/417 ,  H01L29/1004 ,  H01L29/66242 ,  H01L29/7371

    摘要： A heterojunction bipolar transistor (HBT) structure, method of manufacturing the same and design structure thereof are provided. The HBT structure includes a semiconductor substrate having a sub-collector region therein. The HBT structure further includes a collector region overlying a portion of the sub-collector region. The HBT structure further includes an intrinsic base layer overlying at least a portion of the collector region. The HBT structure further includes an extrinsic base layer adjacent to and electrically connected to the intrinsic base layer. The HBT structure further includes an isolation region extending vertically between the extrinsic base layer and the sub-collector region. The HBT structure further includes an emitter overlying a portion of the intrinsic base layer. The HBT structure further includes a collector contact electrically connected to the sub-collector region. The collector contact advantageously extends through at least a portion of the extrinsic base layer.

    摘要翻译： 提供异质结双极晶体管（HBT）结构，其制造方法及其设计结构。 HBT结构包括其中具有亚集电极区域的半导体衬底。 HBT结构还包括覆盖子集电极区域的一部分的集电极区域。 HBT结构还包括覆盖集电极区域的至少一部分的本征基极层。 HBT结构还包括与本征基极层相邻并电连接的外部基极层。 HBT结构还包括在外部基极层和副集电极区之间垂直延伸的隔离区。 HBT结构还包括覆盖本征基极层的一部分的发射极。 HBT结构还包括电连接到子集电极区的集电极触点。 收集器触点有利地延伸穿过外部基极层的至少一部分。

    On-chip transmission line structures with balanced phase delay
    42.
    发明授权
    On-chip transmission line structures with balanced phase delay 有权
    具有平衡相位延迟的片上传输线结构

    公开(公告)号：US08860191B2

    公开(公告)日：2014-10-14

    申请号：US13168512

    申请日：2011-06-24

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    IPC分类号： H01L23/66 ,  H01P1/18 ,  H01L23/522

    CPC分类号： H01L23/5222 ,  H01L23/5225 ,  H01L23/66 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01P1/184 ,  Y10T29/49117 ,  H01L2924/00

    摘要： A transmission wiring structure, associated design structure and associated method for forming the same. A structure is disclosed having: a plurality of wiring levels formed on a semiconductor substrate; a pair of adjacent first and second signal lines located in the wiring levels, wherein the first signal line comprises a first portion formed on a first wiring level and a second portion formed on a second wiring level; a primary dielectric structure having a first dielectric constant located between the first portion and a ground shield; and a secondary dielectric structure having a second dielectric constant different than the first dielectric constant, the secondary dielectric structure located between the second portion and the ground shield, and the second dielectric layer extending co-planar with the second portion and having a length that is substantially the same as the second portion.

    摘要翻译： 一种传输线路结构，相关设计结构及其相关方法。 公开了一种结构，其具有：形成在半导体衬底上的多个布线层; 位于布线层中的一对相邻的第一和第二信号线，其中第一信号线包括形成在第一布线层上的第一部分和形成在第二布线层上的第二部分; 第一介电结构，其具有位于第一部分和接地屏蔽之间的第一介电常数; 以及具有不同于所述第一介电常数的第二介电常数的次级介电结构，所述第二介电结构位于所述第二部分和所述接地屏蔽之间，并且所述第二电介质层与所述第二部分共面延伸并且具有长度为 基本上与第二部分相同。

    Structure for on chip shielding structure for integrated circuits or devices on a substrate
    44.
    发明授权
    Structure for on chip shielding structure for integrated circuits or devices on a substrate 有权
    用于集成电路或基板上的器件的片上屏蔽结构的结构

    公开(公告)号：US08566759B2

    公开(公告)日：2013-10-22

    申请号：US12046750

    申请日：2008-03-12

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu

    IPC分类号： G06F17/50

    CPC分类号： G01R1/18 ,  G01R31/2851 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/665 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/19051 ,  H01L2924/3011 ,  H01L2924/00

    摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure comprises: a conductive structure surrounding and accommodating a circuit or a circuit device arranged on a substrate and at least one feed through capacitor and one transmission line associated with the conductive structure and providing the power supply and signals to the circuit or circuit device respectively. The design structure also comprises a shielding structure surrounding a circuit or a circuit device arranged on a substrate and at least one feed through capacitor or a transmission line arranged on a side of the shielding structure.

    摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括：围绕和容纳布置在基板上的电路或电路装置的导电结构以及与导电结构相关联的至少一个馈电电容器和一个传输线，并将电源和信号提供给电路或电路装置 分别。 该设计结构还包括围绕设置在基板上的电路或电路装置的屏蔽结构以及布置在屏蔽结构侧的电容器或传输线的至少一个馈电。

    METHOD OF OPTIMIZING AN OPTICAL PARAMETRIC MODEL FOR STRUCTURAL ANALYSIS USING OPTICAL CRITICAL DIMENSION (OCD) METROLOGY
    45.
    发明申请
    METHOD OF OPTIMIZING AN OPTICAL PARAMETRIC MODEL FOR STRUCTURAL ANALYSIS USING OPTICAL CRITICAL DIMENSION (OCD) METROLOGY 有权
    使用光学关键尺寸（OCD）方法优化结构分析的光学参数模型的方法

    公开(公告)号：US20120323356A1

    公开(公告)日：2012-12-20

    申请号：US13164398

    申请日：2011-06-20

    申请人： Thaddeus G. Dziura ,  Yung-Ho Chuang ,  Bin-Ming Benjamin Tsai ,  Xuefeng Liu ,  John J. Hench

    发明人： Thaddeus G. Dziura ,  Yung-Ho Chuang ,  Bin-Ming Benjamin Tsai ,  Xuefeng Liu ,  John J. Hench

    IPC分类号： G06F19/00 ,  G06F17/50

    CPC分类号： G01B11/24 ,  G01B2210/56 ,  G01N21/47 ,  G01N21/956 ,  G01N2021/95615 ,  G03F7/70625 ,  G06F17/5009

    摘要： Optimization of optical parametric models for structural analysis using optical critical dimension metrology is described. A method includes determining a first optical model fit for a parameter of a structure. The first optical model fit is based on a domain of quantities for a first model of the structure. A first near optical field response is determined for a first quantity of the domain of quantities and a second near optical field response is determined for a second, different quantity of the domain of quantities. The first and second near optical field responses are compared to locate a common region of high optical field intensity for the parameter of the structure. The first model of the structure is modified to provide a second, different model of the structure. A second, different optical model fit is determined for the parameter of the structure based on the second model of the structure.

    摘要翻译： 描述了使用光学关键尺寸度量结构分析的光学参数模型的优化。 一种方法包括确定适合结构参数的第一光学模型。 第一个光学模型拟合是基于结构的第一个模型的数量域。 对于第一量的量域确定第一近场光响应，并且针对量的第二个不同数量的量确定第二近场光响应。 比较第一和第二近场光响应，以定位用于结构参数的高光场强度的公共区域。 该结构的第一个模型被修改以提供第二个不同的结构模型。 基于结构的第二个模型，确定结构参数的第二个不同的光学模型拟合。

    Integrated millimeter wave antenna and transceiver on a substrate
    46.
    发明授权
    Integrated millimeter wave antenna and transceiver on a substrate 有权
    集成毫米波天线和收发器在基板上

    公开(公告)号：US08232920B2

    公开(公告)日：2012-07-31

    申请号：US12187442

    申请日：2008-08-07

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu

    IPC分类号： H01Q1/38 ,  H01Q1/40

    CPC分类号： H01Q1/2283 ,  H01Q1/40 ,  H01Q9/26 ,  H01Q9/285 ,  H01Q19/108 ,  H01Q19/30

    摘要： A semiconductor chip integrating a transceiver, an antenna, and a receiver is provided. The transceiver is located on a front side of a semiconductor substrate. A through substrate via provides electrical connection between the transceiver and the receiver located on a backside of the semiconductor substrate. The antenna connected to the transceiver is located in a dielectric layer located on the front side of the substrate. The separation between the reflector plate and the antenna is about the quarter wavelength of millimeter waves, which enhances radiation efficiency of the antenna. An array of through substrate dielectric vias may be employed to reduce the effective dielectric constant of the material between the antenna and the reflector plate, thereby reducing the wavelength of the millimeter wave and enhance the radiation efficiency. A design structure for designing, manufacturing, or testing a design for such a semiconductor chip is also provided.

    摘要翻译： 提供集成收发器，天线和接收器的半导体芯片。 收发器位于半导体衬底的前侧。 通过基底通孔提供收发器和位于半导体衬底背面的接收器之间的电连接。 连接到收发器的天线位于位于基板正面的电介质层中。 反射板与天线之间的间隔大约是毫米波的四分之一波长，这提高了天线的辐射效率。 可以采用贯穿衬底电介质通孔的阵列来降低天线和反射板之间材料的有效介电常数，由此减小毫米波的波长并提高辐射效率。 还提供了用于设计，制造或测试这种半导体芯片的设计的设计结构。

    Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate
    47.
    发明授权
    Semiconductor structure including a high performance FET and a high voltage FET on a SOI substrate 有权
    在SOI衬底上包括高性能FET和高电压FET的半导体结构

    公开(公告)号：US08120110B2

    公开(公告)日：2012-02-21

    申请号：US12188381

    申请日：2008-08-08

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Zhenrong Jin ,  Xuefeng Liu ,  Yun Shi

    IPC分类号： H01L27/12

    CPC分类号： H01L27/088 ,  H01L21/823462 ,  H01L21/823481 ,  H01L27/1207

    摘要： A first field effect transistor includes a gate dielectric and a gate electrode located over a first portion of a top semiconductor layer in a semiconductor-on-insulator (SOI) substrate. A second field effect transistor includes a portion of a buried insulator layer and a source region and a drain region located underneath the buried insulator layer. In one embodiment, the gate electrode of the second field effect transistor is a remaining portion of the top semiconductor layer. In another embodiment, the gate electrode of the second field effect transistor is formed concurrently with the gate electrode of the first field effect transistor by deposition and patterning of a gate electrode layer. The first field effect transistor may be a high performance device and the second field effect transistor may be a high voltage device. A design structure for the semiconductor structure is also provided.

    摘要翻译： 第一场效应晶体管包括栅极电介质和位于绝缘体上半导体（SOI））衬底中顶部半导体层的第一部分上方的栅电极。 第二场效应晶体管包括掩埋绝缘体层的一部分和位于掩埋绝缘体层下方的源区和漏区。 在一个实施例中，第二场效应晶体管的栅电极是顶部半导体层的剩余部分。 在另一个实施例中，第二场效应晶体管的栅极通过栅极电极层的沉积和图案化与第一场效应晶体管的栅电极同时形成。 第一场效应晶体管可以是高性能器件，第二场效应晶体管可以是高电压器件。 还提供了用于半导体结构的设计结构。

    Method for forming an on-chip high frequency electro-static discharge device
    49.
    发明授权
    Method for forming an on-chip high frequency electro-static discharge device 有权
    用于形成片上高频静电放电装置的方法

    公开(公告)号：US07915158B2

    公开(公告)日：2011-03-29

    申请号：US12144071

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H01L21/4763

    CPC分类号： H01L21/7682 ,  H01L21/3148 ,  H01L21/318 ,  H01L21/3185 ,  H01L27/0248

    摘要： A method for forming an on-chip high frequency electro-static discharge device is described. In one embodiment, a wafer with a multi-metal level wiring is provided. The wafer includes a first dielectric layer with more than one electrode formed therein, a second dielectric layer disposed over the first dielectric layer with more than one electrode formed therein and more than one via connecting the more than one electrode in the first dielectric layer to a respective more than one electrode in the second dielectric layer. The more than one via is misaligned a predetermined amount with the more than one electrodes in the first dielectric layer and the second dielectric layer. The at least one of the misaligned vias forms a narrow gap with another misaligned via. A cavity trench is formed through the second dielectric layer between the narrow gap that separates the misaligned vias.

    摘要翻译： 描述形成片上高频静电放电装置的方法。 在一个实施例中，提供具有多金属层布线的晶片。 该晶片包括：第一电介质层，其中形成有多于一个电极;第二电介质层，设置在第一电介质层上，其中形成有多于一个电极，多个通孔将第一介电层中的多于一个的电极连接到 在第二介电层中分别有一个以上的电极。 多于一个通孔与第一介电层和第二介电层中的多于一个的电极不对准预定量。 至少一个不对齐的通孔与另一个不对齐的通孔形成了狭窄的间隙。 在分隔未对准的通孔的窄间隙之间通过第二介电层形成腔沟槽。

    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE
    50.
    发明申请
    DESIGN STRUCTURE FOR AN ON-CHIP HIGH FREQUENCY ELECTRO-STATIC DISCHARGE DEVICE 失效
    片上高频电子放电装置的设计结构

    公开(公告)号：US20090316313A1

    公开(公告)日：2009-12-24

    申请号：US12144084

    申请日：2008-06-23

    申请人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    发明人： Hanyi Ding ,  Kai D. Feng ,  Zhong-Xiang He ,  Xuefeng Liu ,  Anthony K. Stamper

    IPC分类号： H02H9/00 ,  G06F17/50

    CPC分类号： G06F17/5068 ,  H01L23/60 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A design structure for an on-chip high frequency electro-static discharge device is described. In one embodiment, the electro-static discharge device comprises a substrate and multiple metal level layers disposed on the substrate. Each metal level comprises more than one electrode formed therein and more than one via connecting with some of the electrodes in adjacent metal levels. The device further includes a gap formed about one of the metal level layers, wherein the gap is hermetically sealed to provide electro-static discharge protection for the integrated circuit.

    摘要翻译： 描述了片上高频静电放电装置的设计结构。 在一个实施例中，静电放电装置包括衬底和设置在衬底上的多个金属层。 每个金属层包括多于一个电极，其中形成有多个电极，并且多个通孔与相邻金属层中的一些电极连接。 所述装置还包括围绕所述金属层之一形成的间隙，其中所述间隙被气密密封以为所述集成电路提供静电放电保护。