公开(公告)号：US08923083B2

公开(公告)日：2014-12-30

申请号：US13592437

申请日：2012-08-23

申请人： Takao Akaogi ,  Tony Chan

发明人： Takao Akaogi ,  Tony Chan

IPC分类号： G11C29/00

CPC分类号： G11C29/025 ,  G11C2029/1204

摘要： A method of identifying a damaged bitline address in a non-volatile memory device is introduced. The non-volatile memory device includes a memory cell array and a plurality of bit lines crossing the memory cell array. Each bit line has a first end and a second end. The bit lines are divided into a first group and a second group. The method includes applying a source voltage (charging) or ground voltage (discharging) to a specific group of bit lines, testing the bit lines in two testing stages (open-circuit testing and short-circuit testing) by the principle that no damaged bit line can be charged or discharged, and acquiring an address data of a damaged bit line according to a status data stored in a page buffering circuit and related to whether a bit line is damaged, thereby dispensing with a calculation process for estimating the address of the damaged bit line.

摘要翻译： 介绍了识别非易失性存储器件中损坏的位线地址的方法。 非易失性存储器件包括存储单元阵列和与存储单元阵列交叉的多个位线。 每个位线具有第一端和第二端。 位线被分成第一组和第二组。 该方法包括将源电压（充电）或接地电压（放电）施加到特定的位线组，在两个测试阶段（开路测试和短路测试）中测试位线，原理是没有损坏的位 线路可以被充电或放电，并且根据存储在页面缓冲电路中的状态数据获取损坏的位线的地址数据，并且与位线是否损坏有关，从而分配用于估计位线的地址的计算处理 损坏的位线。

公开(公告)号：US07986579B2

公开(公告)日：2011-07-26

申请号：US12030485

申请日：2008-02-13

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G11C7/04

CPC分类号： G11C7/04 ,  G11C7/067 ,  G11C16/26 ,  G11C2207/063

摘要： A device, and corresponding method, includes a temperature dependent bias generator to generate a voltage that is applied to a control gate of a sense amplifier. By applying the temperature dependent bias signal to the sense amplifier, a substantially temperature independent discharge time can be achieved at a sense node of a sense amplifier.

摘要翻译： 一种器件和相应的方法包括温度依赖偏置发生器，以产生施加到读出放大器的控制栅极的电压。 通过将温度依赖偏置信号应用于感测放大器，可以在感测放大器的感测节点处实现基本上温度无关的放电时间。

公开(公告)号：US07312641B2

公开(公告)日：2007-12-25

申请号：US11024257

申请日：2004-12-28

申请人： Takao Akaogi ,  Sameer Wadhwa ,  Michael Achter ,  Bhimachar Venkatesh

发明人： Takao Akaogi ,  Sameer Wadhwa ,  Michael Achter ,  Bhimachar Venkatesh

IPC分类号： G01R19/00 ,  G11C7/00

CPC分类号： G11C7/062 ,  G11C2207/063 ,  H03F3/345 ,  H03F3/45183 ,  H03F3/45475 ,  H03F2200/462 ,  H03F2200/78

摘要： A sense amplifier includes a reference voltage generator for generating a reference output voltage and a core output voltage generator for generating a core output voltage. The core output voltage generator includes a core front-end stage and a core back-end stage or includes a plurality of amplifier transistors each conducting a portion of a core current through a current conducting device such as core cell. The sizes and/or connections of transistors of such components result in high voltage swing and thus high sensitivity of the sense amplifier.

摘要翻译： 读出放大器包括用于产生参考输出电压的参考电压发生器和用于产生核心输出电压的核心输出电压发生器。 核心输出电压发生器包括核心前端级和核心后端级，或者包括多个放大器晶体管，每个放大器晶体管通过诸如核心单元之类的电流传导器件导通核心电流的一部分。 这种组件的晶体管的尺寸和/或连接导致高电压摆动，从而导致读出放大器的高灵敏度。

公开(公告)号：US20070064493A1

公开(公告)日：2007-03-22

申请号：US11229664

申请日：2005-09-20

申请人： Takao Akaogi ,  Guowei Wang

发明人： Takao Akaogi ,  Guowei Wang

IPC分类号： G11C16/04

CPC分类号： G11C16/0491 ,  G11C16/0475 ,  G11C16/10

摘要： Non-volatile memory, such as Flash memory, is programmed by writing a window of information to memory. The programmed/non-programmed state of each memory cell may be dynamically determined for each window and stored as an indication bit. These techniques can provide for improved average power drain and a reduced maximum current per window during programming.

摘要翻译： 诸如闪存的非易失性存储器通过将信息窗口写入存储器来编程。 可以为每个窗口动态地确定每个存储器单元的编程/非编程状态并将其存储为指示位。 这些技术可以在编程期间提供改善的平均功率消耗和减小每个窗口的最大电流。

公开(公告)号：US20060203598A1

公开(公告)日：2006-09-14

申请号：US11076252

申请日：2005-03-08

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G11C8/00

CPC分类号： G11C16/08 ,  G11C8/08

摘要： A decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on. The decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls the driving devices to turn on or off. Also, a capacitor coupled to the common node increases the voltage at the common node from an initial boost voltage to a final boost voltage. Thus, a line of a memory device is driven to a boost voltage with minimized area and wiring complexity.

摘要翻译： 用于存储器件的解码器包括驱动器件，每个驱动器件在接通时将相应的线电压施加到存储器件的相应线路。 解码器还包括在公共节点处耦合到多个驱动装置的控制装置，用于产生控制驱动装置打开或关闭的电压。 此外，耦合到公共节点的电容器将公共节点处的电压从初始升压电压增加到最终升压电压。 因此，存储器件的一行被驱动到具有最小面积和布线复杂度的升压电压。

公开(公告)号：US06621761B2

公开(公告)日：2003-09-16

申请号：US09829518

申请日：2001-04-09

申请人： Takao Akaogi ,  Lee Cleveland ,  Kendra Nguyen

发明人： Takao Akaogi ,  Lee Cleveland ,  Kendra Nguyen

IPC分类号： G06C800

CPC分类号： G11C7/1018 ,  G11C7/1072

摘要： A burst mode architecture to provide burst mode access to a plurality of data words in a flash memory is described. The burst mode architecture includes a first circuit, a control circuit coupled to the first circuit, and a data buffer selectively coupled to the first circuit by the control circuit. The first circuit accesses a plurality of data words, beginning with an initial access of a first data word and a second data word. The control circuit generates a timing signal having pulses and a second signal. The second signal is generated upon completion of the initial access of the first data word and the second data word. The first circuit follows the initial access with subsequent accesses of the plurality of data words responsively to the second signal and the timing signal. The data buffer has an output and produces the first data word at the output and successively produces, with each successive pulse of the timing signal following an initial period of time, the second data word, and subsequent data words at the output. The subsequent data words correspond to the subsequent accesses of the plurality of data words.

公开(公告)号：US06618288B2

公开(公告)日：2003-09-09

申请号：US10265106

申请日：2002-10-07

申请人： Takao Akaogi ,  Yasushi Kasa

发明人： Takao Akaogi ,  Yasushi Kasa

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

公开(公告)号：US06566938B2

公开(公告)日：2003-05-20

申请号：US09916972

申请日：2001-07-27

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G05F110

CPC分类号： G05F1/618

摘要： A system for a constant current source circuit utilizing CMOS technology. The system includes a constant current source circuit that includes a bias circuit that outputs a bias signal and a switch circuit that has a switch input coupled to receive the bias signal, a switch output, and a switch control that is coupled to receive an input signal. The current source circuit also includes an output circuit that has a first input coupled to the switch output and a second input coupled to the input signal. The output circuit provides an output signal that has constant current.

公开(公告)号：US06563738B2

公开(公告)日：2003-05-13

申请号：US10150017

申请日：2002-05-20

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

公开(公告)号：US06542415B2

公开(公告)日：2003-04-01

申请号：US09932077

申请日：2001-08-17

申请人： Takao Akaogi

发明人： Takao Akaogi

IPC分类号： G11C700

CPC分类号： G11C8/18

摘要： A signal generator for generating a kickb signal used to reset a boost signal used to operate a memory device. The signal generator includes an address detector that receives one or more address lines and a clock signal to produce a detector output. A switch circuit is also included that receives the detector output, the clock signal and a feedback signal to produce a switch output. A delay circuit is coupled to receive the switch output to produce a delayed switch output, and an output circuit is coupled to receive the switch output and the delayed switch output to produce the kickb signal, where the kickb signal forms the feedback signal.

摘要翻译： 一种用于产生用于复位用于操作存储器件的升压信号的脚踏信号的信号发生器。 信号发生器包括地址检测器，其接收一个或多个地址线和时钟信号以产生检测器输出。 还包括接收检测器输出，时钟信号和反馈信号以产生开关输出的开关电路。 延迟电路被耦合以接收开关输出以产生延迟的开关输出，并且输出电路被耦合以接收开关输出和延迟的开关输出以产生脚踏信号，其中脚踏信号形成反馈信号。