公开(公告)号：US06563738B2

公开(公告)日：2003-05-13

申请号：US10150017

申请日：2002-05-20

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

公开(公告)号：US5452251A

公开(公告)日：1995-09-19

申请号：US79738

申请日：1993-06-22

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C11/40

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US5815440A

公开(公告)日：1998-09-29

申请号：US822036

申请日：1997-03-24

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2.sup.n word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任一个有缺陷时，选择在2n个字线之外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US06611464B2

公开(公告)日：2003-08-26

申请号：US10265233

申请日：2002-10-07

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita ,  Shouichi Kawamura

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device has 2n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2m (n>m) word lines among the 2n word lines, and a second unit for not selecting a block of 2k (m>k) word lines among the 2m word lines. The second unit does not select the block of 2k word lines, and selects a block of 2k word lines prepared outside the 2n word lines when any one of the 2k word lines among the 2m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

公开(公告)号：US5666314A

公开(公告)日：1997-09-09

申请号：US432723

申请日：1995-06-06

申请人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

发明人： Takao Akaogi ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano ,  Hiromi Kawashima ,  Minoru Yamashita

IPC分类号： G11C5/14 ,  G11C7/06 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/34 ,  G11C29/00 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C7/00

CPC分类号： G11C29/80 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C2029/5004 ,  G11C29/88

摘要： A semiconductor memory device has 2.sup.n word lines, a plurality of bit lines, a plurality of nonvolatile memory cells disposed at each intersection of the word lines and the bit lines, a write circuit for writing data to a memory cell located at an intersection of selected ones of the word lines and the bit lines, and a sense amplifier for reading data out of the memory cells. Further, the semiconductor memory device comprises a first unit for simultaneously selecting a block of 2.sup.m (n>m) word lines among the 2.sup.n word lines, and a second unit for not selecting a block of 2.sup.k (m>k) word lines among the 2.sup.m word lines. The second unit does not select the block of 2.sup.k word lines, and selects a block of 2.sup.k word lines prepared outside the 2" word lines when any one of the 2.sup.k word lines among the 2.sup.m word lines is defective. Consequently, redundant word lines are effectively employed, write and verify operations are stable, and thereby the yield and performance of the semiconductor memory device are improved.

摘要翻译： 半导体存储器件具有2n字线，多个位线，设置在字线和位线的每个交叉处的多个非易失性存储器单元，写入电路用于将数据写入位于所选择的交叉点的存储器单元 字线和位线中的一个以及用于从存储器单元读出数据的读出放大器。 此外，半导体存储装置包括：第一单元，用于同时选择2n个字线中的2m（n> m）个字线的块;以及第二单元，用于不选择2k（m> k）个字线的块， 2m字线。 第二单元不选择2k个字线的块，并且当2m个字线中的任何2k个字线中的任何一个有缺陷时，选择2K字线以外准备的2k个字线的块。 因此，有效地使用冗余字线，写入和验证操作是稳定的，从而提高半导体存储器件的产量和性能。

公开(公告)号：US06646920B2

公开(公告)日：2003-11-11

申请号：US10265100

申请日：2002-10-07

申请人： Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano

发明人： Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano

IPC分类号： G11C1604

CPC分类号： G11C29/80 ,  G11C5/145 ,  G11C7/067 ,  G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/04 ,  G11C16/0416 ,  G11C16/08 ,  G11C16/10 ,  G11C16/107 ,  G11C16/12 ,  G11C16/16 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/3436 ,  G11C16/3445 ,  G11C16/3459 ,  G11C16/3472 ,  G11C16/3481 ,  G11C29/028 ,  G11C29/34 ,  G11C29/46 ,  G11C29/50 ,  G11C29/50004 ,  G11C29/802 ,  G11C29/82 ,  G11C29/88 ,  G11C2029/5004

摘要： A semiconductor memory device includes a plurality of word lines and a plurality of bit lines. A plurality of memory cells, each formed of a MIS transistor, are disposed at intersections of the word lines and the bit lines. The threshold voltages of the MIS transistors being externally electrically controllable according to charges to be injected to floating gates thereof. The floating gates of the MIS transistors being simultaneously discharged to collectively erase the memory cells. A first row decoder applies a normal voltage to a selected word line to select memory cells connected to the selected word line, when reading data. A second row decoder applies a predetermined source voltage to sources of memory cells connected to the selected word line, and applies an unselected state establishing voltage to the sources of memory cells, including those overerased by the collective erasing, connected to unselected word lines, when reading data.

摘要翻译： 半导体存储器件包括多个字线和多个位线。 每个由MIS晶体管形成的多个存储单元设置在字线和位线的相交处。 MIS晶体管的阈值电压根据要注入其浮动栅极的电荷在外部可电控制。 MIS晶体管的浮置栅极同时放电，以共同擦除存储单元。 当读取数据时，第一行解码器将正常电压施加到所选择的字线以选择连接到所选字线的存储器单元。 第二行解码器将预定的源电压施加到连接到所选字线的存储器单元的源，并且将未选择的状态建立电压施加到存储单元的源，包括连接到未选择的字线的由集体擦除过渡的存储单元的源 阅读数据。

公开(公告)号：US5581107A

公开(公告)日：1996-12-03

申请号：US358604

申请日：1994-12-14

申请人： Shouichi Kawamura ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano

发明人： Shouichi Kawamura ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano

IPC分类号： H01L21/8247 ,  G11C16/04 ,  G11C16/14 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/80 ,  H01L27/02 ,  H01L29/78

CPC分类号： G11C16/04 ,  G11C16/14

摘要： An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.

公开(公告)号：US5406524A

公开(公告)日：1995-04-11

申请号：US186118

申请日：1994-01-25

申请人： Shouichi Kawamura ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano

发明人： Shouichi Kawamura ,  Nobuaki Takashina ,  Yasushi Kasa ,  Kiyoshi Itano

IPC分类号： H01L21/8247 ,  G11C16/04 ,  G11C16/14 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C13/00

CPC分类号： G11C16/04 ,  G11C16/14

摘要： An object of the present invention is to ease the dielectric strength requirements for transistors forming power supply circuits or the like. A nonvolatile semiconductor memory of the present invention includes a plurality of memory cells, each of which is composed of a floating gate, a control gate, a drain, and a source, and a negative voltage generating means whose generated negative voltage is applied to the control gate for drawing a charge stored in the floating gate into a channel or the source when stored data is erased electrically. The nonvolatile memory of the present invention further includes positive erasure voltage generating means, and a positive voltage higher than a conventional supply voltage generated by the positive erasure voltage generating means is applied to the channel or the source.

摘要翻译： 本发明的目的是减轻形成电源电路等的晶体管的介电强度要求。 本发明的非易失性半导体存储器包括多个存储单元，每个存储单元由浮置栅极，控制栅极，漏极和源极组成，负电压产生装置的负电压施加到 当存储的数据被电擦除时，用于将存储在浮动栅极中的电荷绘制成通道或源的控制门。 本发明的非易失性存储器还包括正的擦除电压产生装置，并且将比由正的擦除电压产生装置产生的常规电源电压高的正电压施加到信道或源。

公开(公告)号：US5237530A

公开(公告)日：1993-08-17

申请号：US795147

申请日：1991-11-20

申请人： Nobuaki Takashina ,  Takao Akaogi ,  Masanobu Yoshida

发明人： Nobuaki Takashina ,  Takao Akaogi ,  Masanobu Yoshida

IPC分类号： G11C17/00 ,  G11C29/08 ,  G11C29/34 ,  G11C29/52

CPC分类号： G11C29/34 ,  G11C29/08 ,  G11C29/52

摘要： An erasable non-volatile semiconductor memory device has a plurality of erasable non-volatile memory cells each comprising two cell transistors, the write statuses of which are inverted, and detects the write status of each memory cell by a differential type detection circuit through first and second bit lines connected to the two cell transistors. Further, the erasable non-volatile semiconductor memory device sets all cell transistors constructing a plurality of the memory cells to the erasing status or write status in entirety, and controls the connection of the first and second bit lines for executing the read/write test. Therefore, the erasable non-volatile semiconductor memory device according to the present invention can reduce the erasing process cycles, which requires a long time, falsely read out the "0" data and "1" data without writing actual data into each memory cell to shorten the test time, and thus can supply a low price product.

摘要翻译： 可擦除非易失性半导体存储器件具有多个可擦除非易失性存储单元，每个可擦除非易失性存储单元包括两个单元晶体管，其写状态被反相，并且通过差分型检测电路首先检测每个存储单元的写状态， 连接到两个单元晶体管的第二位线。 此外，可擦除非易失性半导体存储器件将构成多个存储单元的所有单元晶体管全部设置为擦除状态或写入状态，并且控制用于执行读/写测试的第一和第二位线的连接。 因此，根据本发明的可擦除非易失性半导体存储器件可以减少擦除处理周期，这需要很长时间，错误地读出“0”数据和“1”数据，而不将实际数据写入每个存储器单元 缩短测试时间，从而可以提供低价格的产品。

公开(公告)号：US5959887A

公开(公告)日：1999-09-28

申请号：US28768

申请日：1998-02-24

申请人： Nobuaki Takashina ,  Masanobu Yoshida

发明人： Nobuaki Takashina ,  Masanobu Yoshida

IPC分类号： G11C16/02 ,  G11C7/10 ,  G11C7/18 ,  G11C16/16 ,  H01L21/82 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C16/04 ,  G11C7/00

CPC分类号： G11C16/16 ,  G11C7/1042 ,  G11C7/18

摘要： An electrically erasable programmable nonvolatile semiconductor memory has a memory cell array having a plurality of memory cells which are placed as a matrix configuration. The memory cell array is divided into a plurality of memory cell blocks having required sizes by splitting each bit line of the memory cell array at: an optional position. This memory provides a dual operation function without complicating the circuit thereof or increasing the chip size thereof. The bit structure of each memory cell block to be divided from the memory cell array is variable.

摘要翻译： 电可擦除可编程非易失性半导体存储器具有存储单元阵列，其具有放置为矩阵配置的多个存储单元。 存储单元阵列被分成具有所需大小的多个存储单元块，通过在可选位置分割存储单元阵列的每个位线。 该存储器提供双重操作功能，而不使其电路复杂化或增加其芯片尺寸。 要从存储单元阵列中分割的每个存储单元块的位结构是可变的。