公开(公告)号：US5107141A

公开(公告)日：1992-04-21

申请号：US604454

申请日：1990-10-29

申请人： Kazuo Yano ,  Mitsuru Hiraki ,  Hisayuki Higuchi ,  Suguru Tachibana ,  Makoto Suzuki ,  Katsuhiro Shimohigashi

发明人： Kazuo Yano ,  Mitsuru Hiraki ,  Hisayuki Higuchi ,  Suguru Tachibana ,  Makoto Suzuki ,  Katsuhiro Shimohigashi

IPC分类号： H03K19/00 ,  H03K19/013 ,  H03K19/0944

CPC分类号： H03K19/0013 ,  H03K19/0136 ,  H03K19/09448

摘要： An output circuit portion of a BiCMOS logic circuit adapted to operating on a low voltage has an npn transistor Q5 connected between the power source Vcc and an output N6, and has an npn transistor Q6 connected between the output N6 and ground potential GND. The base of the npn transistor Q5 is driven by the drain output of p-channel MOSFETs MP3, MP4, and the base of the npn transistor Q6 is driven by the drain output of p-channel MOSFET QP5. When the power source voltage Vcc drops, the voltage applied between the drain and the source of MOSFET MP5 becomes small by the effect of V.sub.BE of the transistor Q6, but the drain current of the MOSFET MP5 changes little. Therefore, the BiCMOS circuit operates at high speeds (see FIG. 1) even when the power source voltage drops.

摘要翻译： 适用于低电压工作的BiCMOS逻辑电路的输出电路部分具有连接在电源Vcc和输出N6之间的npn晶体管Q5，并具有连接在输出N6和地电位GND之间的npn晶体管Q6。 npn晶体管Q5的基极由p沟道MOSFET MP3，MP4的漏极输出驱动，npn晶体管Q6的基极由p沟道MOSFET QP5的漏极输出驱动。 当电源电压Vcc下降时，通过晶体管Q6的VBE的影响，施加在MOSFET MP5的漏极和源极之间的电压变小，但MOSFET MP5的漏极电流变化较小。 因此，即使当电源电压下降时，BiCMOS电路也以高速工作（参见图1）。

公开(公告)号：US5041892A

公开(公告)日：1991-08-20

申请号：US522826

申请日：1990-05-14

申请人： Kazuo Yano ,  Masaaki Aoki ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi

发明人： Kazuo Yano ,  Masaaki Aoki ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/36 ,  H01L29/66 ,  H01L29/732

CPC分类号： H01L29/66992 ,  H01L27/0623 ,  H01L29/36

摘要： In a homo-junction bipolar transistor suitable for a low temperature operation below 200 K. (particularly below 77 K.), the maximum value of the impurity concentration of an intrinsic base region is set to be at least 1.times.10.sup.18 /cm.sup.3 and the impurity concentration of an emitter region is set to a value lower than this maximum value. Thus, a base resistance can be reduced and a high speed operation becomes possible. Furthermore, bandgap narrowing develops in the intrinsic base region and a common-emitter current gain in the low temperature operation can be kept at a sufficient value. When this homo-junction bipolar transistor is formed together with complementary insulated gate field effect transistors on the surface of a semiconductor substrate, there can be obtained a Bi-CMOS device capable of a high speed operation even in the low temperature operation.

公开(公告)号：US5021944A

公开(公告)日：1991-06-04

申请号：US376245

申请日：1989-07-06

申请人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Shoji Hanamura

发明人： Katsuro Sasaki ,  Katsuhiro Shimohigashi ,  Shoji Hanamura

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04

CPC分类号： G11C29/846

摘要： A method and apparatus for quickly masking defective memory elements with substitute memory elements includes first and second memory blocks. The first memory block includes a first memory array and a second spare memory array. The second memory block includes a second memory array and a first spare memory array. A first word from the first memory array is selected concurrently with a first substitute word from the first spare memory. An address signal is decoded and then compared with data representative of a defective word. In the event it is determined, as a result of this comparison, that the first word is defective, the first substitute word is then communicated to a common data bus. Alternatively, the first word is communicated to the common data bus.

摘要翻译： 用替代存储器元件快速掩蔽有缺陷的存储器元件的方法和装置包括第一和第二存储器块。 第一存储器块包括第一存储器阵列和第二备用存储器阵列。 第二存储器块包括第二存储器阵列和第一备用存储器阵列。 与来自第一备用存储器的第一替代字同时选择来自第一存储器阵列的第一个字。 地址信号被解码，然后与表示有缺陷的字的数据进行比较。 在确定的情况下，作为该比较的结果，第一个字是有缺陷的，然后第一个替代字被传送到公共数据总线。 或者，第一个字被传送到公共数据总线。

公开(公告)号：US4873672A

公开(公告)日：1989-10-10

申请号：US51715

申请日：1987-05-20

申请人： Jun Etoh ,  Katsuhiro Shimohigashi ,  Kazuyuki Miyazawa ,  Katsutaka Kimura ,  Takesada Akiba

发明人： Jun Etoh ,  Katsuhiro Shimohigashi ,  Kazuyuki Miyazawa ,  Katsutaka Kimura ,  Takesada Akiba

IPC分类号： G11C11/401 ,  G11C11/4072 ,  G11C11/4078 ,  G11C11/409

CPC分类号： G11C11/4078 ,  G11C11/4072

摘要： This invention relates to a semiconductor memory having a high speed operation and a high integration density. When a high integration semiconductor memory is applied to a large scale computer system, storage data must be erased at a high speed for data security. The present invention erases the storage data by a method which is different from the write method of conventional prior art. In the invention, the erasing operation is made by continuously selecting word lines while sense amplifiers are kept in this on-state. The present invention includes a control circuit for attaining such an operation, and can be used for a semiconductor memory implemented in a computer system accessed by a plurality of users.

摘要翻译： 本发明涉及具有高速运算和高集成密度的半导体存储器。 当将高集成半导体存储器应用于大规模计算机系统时，为了数据安全，必须高速擦除存储数据。 本发明通过与传统现有技术的写入方法不同的方法擦除存储数据。 在本发明中，通过在感测放大器保持在该接通状态的同时连续选择字线来进行擦除操作。 本发明包括用于实现这种操作的控制电路，并且可以用于由多个用户访问的计算机系统中实现的半导体存储器。

公开(公告)号：US4747082A

公开(公告)日：1988-05-24

申请号：US76174

申请日：1987-07-21

申请人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

发明人： Osamu Minato ,  Toshiaki Masuhara ,  Katsuhiro Shimohigashi ,  Shoji Hanamura ,  Shigeru Honjyo ,  Nobuyuki Moriwaki ,  Fumio Kojima

IPC分类号： G11C11/406 ,  G11C8/00

CPC分类号： G11C11/406

摘要： A semiconductor memory is provided with automatic refresh means including a timer, a refresh counter and a refresh buffer each formed on a semiconductor chip mounted with an asynchronous memory, for automatically performing a periodic refresh operation on the basis of a basic clock signal which is generated in response to the detection of a logical change in the output of the refresh counter. The automatic refresh counter includes means for performing one of a read operation and a write operation which are based upon a regular address signal asynchronous with the periodic refresh operation, in preference to the periodic refresh operation.

摘要翻译： 半导体存储器设置有自动刷新装置，包括定时器，刷新计数器和刷新缓冲器，每个形成在安装有异步存储器的半导体芯片上，用于基于生成的基本时钟信号自动执行周期性刷新操作 响应于对刷新计数器的输出的逻辑改变的检测。 自动刷新计数器包括优先于周期性刷新操作执行基于与周期性刷新操作异步的常规地址信号的读操作和写操作之一的装置。

公开(公告)号：US4672586A

公开(公告)日：1987-06-09

申请号：US617919

申请日：1984-06-06

申请人： Katsuhiro Shimohigashi ,  Masaharu Kubo ,  Katsuki Miyauchi ,  Toshiaki Masuhara ,  Osamu Minato

发明人： Katsuhiro Shimohigashi ,  Masaharu Kubo ,  Katsuki Miyauchi ,  Toshiaki Masuhara ,  Osamu Minato

IPC分类号： G11C11/401 ,  G11C5/14 ,  G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  H01L21/822 ,  H01L21/8247 ,  H01L27/04 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C11/406 ,  G11C11/4072 ,  G11C11/4074 ,  G11C5/141

摘要： A semiconductor memory using a dynamic memory device, wherein a battery supplies a power source voltage and a substrate bias voltage when the memory is cut off from an external device, and a refresh control circuit changes in refresh timing of the memory device in accordance with the leakage current of the memory device. The power consumption of the memory can thus be reduced and the data can be kept for an extended period without an external power source.

公开(公告)号：US4592022A

公开(公告)日：1986-05-27

申请号：US756707

申请日：1985-07-19

申请人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Kunihiko Ikuzaki ,  Hiroshi Kawamoto

发明人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Kunihiko Ikuzaki ,  Hiroshi Kawamoto

IPC分类号： G11C11/419 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/04 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  G11C11/40 ,  G11C13/00

CPC分类号： G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/108 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S148/164

摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the data lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

公开(公告)号：US06740958B2

公开(公告)日：2004-05-25

申请号：US10115101

申请日：2002-04-04

申请人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

发明人： Shinji Nakazato ,  Hideaki Uchida ,  Yoshikazu Saito ,  Masahiro Yamamura ,  Yutaka Kobayashi ,  Takahide Ikeda ,  Ryoichi Hori ,  Goro Kitsukawa ,  Kiyoo Itoh ,  Nobuo Tanba ,  Takao Watanabe ,  Katsuhiro Shimohigashi ,  Noriyuki Homma

IPC分类号： H01L2900

CPC分类号： H01L27/0623 ,  H01L27/0214 ,  H01L27/0218 ,  H01L27/0922 ,  H01L27/105 ,  H01L27/10805

摘要： Disclosed is a semiconductor device, such as a semiconductor memory device, having structure wherein invasion of minority carriers from the semiconductor substrate into components of the device, formed on the substrate, can be avoided. The semiconductor memory device can be an SRAM or DRAM, for example, and includes a memory array and peripheral circuit on a substrate. In one aspect of the present invention, a buried layer of the same conductivity type as that of the substrate, but with a higher impurity concentration than that of the substrate, is provided beneath at least one of the peripheral circuit and memory array. A further region can extend from the buried layer, for example, to the surface of the semiconductor substrate, the buried layer and further region in combination acting as a shield to prevent minority carriers from penetrating to the device elements. As a second aspect of the present invention, first carrier absorbing areas (to absorb minority carriers) are located between the memory array and the switching circuit of the peripheral circuit, and second carrier absorbing areas are provided to surround input protective elements of the device. As a third embodiment of the present invention, a plurality of isolation regions of the same conductivity type are provided, with unequal voltages applied to these isolation regions, or unequal voltages applied to the substrate, on the one hand, and to these isolation regions, on the other.

摘要翻译： 公开了一种半导体器件，例如半导体存储器件，其结构可以避免少数载流子从半导体衬底侵入形成在衬底上的器件的部件。 半导体存储器件例如可以是SRAM或DRAM，并且在衬底上包括存储器阵列和外围电路。 在本发明的一个方面中，在外围电路和存储器阵列中的至少一个之下提供与衬底相同的导电类型但具有比衬底的杂质浓度更高的杂质浓度的掩埋层。 另外的区域可以例如从掩埋层延伸到半导体衬底的表面，掩埋层和组合的另外的区域用作屏蔽以防止少数载流子穿透到器件元件。 作为本发明的第二方面，第一载流子吸收区域（以吸收少数载流子）位于存储器阵列和外围电路的开关电路之间，并且第二载流子吸收区域被设置为环绕该器件的输入保护元件。 作为本发明的第三实施例，提供了相同导电类型的多个隔离区域，一方面施加到这些隔离区域的不同电压或施加到基板的不同电压以及这些隔离区域， 在另一。

公开(公告)号：US5808951A

公开(公告)日：1998-09-15

申请号：US951206

申请日：1997-09-17

申请人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Kunihiko Ikuzaki ,  Hiroshi Kawamoto

发明人： Katsuhiro Shimohigashi ,  Hiroo Masuda ,  Kunihiko Ikuzaki ,  Hiroshi Kawamoto

IPC分类号： G11C7/10 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/108 ,  G11C13/00

CPC分类号： G11C7/1048 ,  G11C11/409 ,  G11C11/4091 ,  G11C11/4096 ,  G11C11/4097 ,  H01L23/522 ,  H01L27/108 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A dynamic RAM integrated circuit of the one-element memory cell type is provided with a plurality of data lines, a sense amplifier, a plurality of word lines disposed in a manner to intersect with the data lines, and memory cells disposed at the points of intersection between the data lines and the word lines. The RAM includes a P-type semiconductor substrate and an N-type well region formed in the substrate. The memory cells are disposed within the well, and the sense amplifier, which is connected to the date lines, is constructed of a pair of N-channel MOSFETs formed in the semiconductor substrate and a pair of P-channel MOSFETs formed in the well region.

公开(公告)号：US5550781A

公开(公告)日：1996-08-27

申请号：US381648

申请日：1995-01-31

申请人： Ken Sugawara ,  Shigeru Sakairi ,  Mikio Matoba ,  Toshio Sasaki ,  Katsuhiro Shimohigashi ,  Katsutaka Kimura

发明人： Ken Sugawara ,  Shigeru Sakairi ,  Mikio Matoba ,  Toshio Sasaki ,  Katsuhiro Shimohigashi ,  Katsutaka Kimura

IPC分类号： G11C5/14 ,  G11C8/18 ,  G11C11/406 ,  G11C11/4074 ,  G11C11/40

CPC分类号： G11C8/18 ,  G11C11/406 ,  G11C11/4074 ,  G11C5/141 ,  G11C5/143 ,  G11C5/147

摘要： A memory cartridge having a plurality of dynamic memory units includes an access conversion circuit which converts a static access signal into its inverted signal and an access control circuit which controllably switches between a signal for refreshing each dynamic unit and a signal for external access. The memory cartridge also includes a power switching circuit which switches power from an internal power supply to an external power supply when the memory cartridge is mounted to an external device.

摘要翻译： 具有多个动态存储单元的存储器盒包括将静态访问信号转换为其反相信号的访问转换电路和可控地在用于刷新每个动态单元的信号和用于外部访问的信号之间切换的访问控制电路。 存储盒还包括一个电源切换电路，当存储盒被安装到外部设备时，电源切换电路将电源从内部电源切换到外部电源。