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    Semiconductor integrated circuits with stacked node contact structures and methods of fabricating such devices
    41.
    发明申请
    Semiconductor integrated circuits with stacked node contact structures and methods of fabricating such devices 有权
    具有堆叠节点接触结构的半导体集成电路和制造这种器件的方法

    公开(公告)号：US20050179061A1

    公开(公告)日：2005-08-18

    申请号：US11033432

    申请日：2005-01-11

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L29/417 ,  H01L21/768 ,  H01L21/77 ,  H01L21/8244 ,  H01L21/84 ,  H01L27/06 ,  H01L27/11 ,  H01L27/12 ,  H01L29/41 ,  H01L29/786 ,  H01L27/10

    CPC分类号： H01L27/1214 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

    摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

    SRAM devices having buried layer patterns
    42.
    发明授权
    SRAM devices having buried layer patterns 有权
    具有掩埋层图案的SRAM器件

    公开(公告)号：US07671389B2

    公开(公告)日：2010-03-02

    申请号：US11385473

    申请日：2006-03-21

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L31/112

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

    摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

    Semiconductor integrated circuits with stacked node contact structures
    43.
    发明授权
    Semiconductor integrated circuits with stacked node contact structures 有权
    具有堆叠节点接触结构的半导体集成电路

    公开(公告)号：US07479673B2

    公开(公告)日：2009-01-20

    申请号：US11033432

    申请日：2005-01-11

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L27/02

    CPC分类号： H01L27/1214 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

    摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

    Semiconductor Integrated Circuits With Stacked Node Contact Structures
    44.
    发明申请
    Semiconductor Integrated Circuits With Stacked Node Contact Structures 审中-公开
    具有堆叠节点接触结构的半导体集成电路

    公开(公告)号：US20080023728A1

    公开(公告)日：2008-01-31

    申请号：US11868648

    申请日：2007-10-08

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Kun-Ho Kwak ,  Byung-Jun Hwang

    IPC分类号： H01L27/10

    CPC分类号： H01L27/1214 ,  H01L23/481 ,  H01L27/0688 ,  H01L27/11 ,  H01L27/1108

    摘要： Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.

    摘要翻译： 提供包括薄膜晶体管（TFT）的半导体集成电路和制造这种半导体集成电路的方法。 半导体集成电路可以包括形成在半导体衬底上的体晶体管和体晶体管上的第一层间绝缘层。 下部TFT可以在第一层间绝缘层上，第二层间绝缘层可以在下部TFT上。 上层TFT可以在第二层间绝缘层上，第三层间绝缘层可以在上部TFT上。 本体晶体管的第一杂质区，下TFT的第一杂质区和上TFT的第一杂质区可以通过穿透第一，第二和第三层间绝缘层的节点插塞彼此电连接。

    SRAM devices having buried layer patterns and methods of forming the same
    45.
    发明申请
    SRAM devices having buried layer patterns and methods of forming the same 有权
    具有掩埋层图案的SRAM器件及其形成方法

    公开(公告)号：US20060216886A1

    公开(公告)日：2006-09-28

    申请号：US11385473

    申请日：2006-03-21

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： An SRAM device includes a substrate having at least one cell active region in a cell array region and a plurality of peripheral active regions in a peripheral circuit region, a plurality of stacked cell gate patterns in the cell array region, and a plurality of peripheral gate patterns disposed on the peripheral active regions in the peripheral circuit region. Metal silicide layers are disposed on at least one portion of the peripheral gate patterns and on the semiconductor substrate near the peripheral gate patterns, and buried layer patterns are disposed on the peripheral gate patterns and on at least a portion of the metal silicide layers and the portions of the semiconductor substrate near the peripheral gate patterns. An etch stop layer and a protective interlayer-insulating layer are disposed around the peripheral gate patterns and on the cell array region. Methods of forming an SRAM device are also disclosed.

    摘要翻译： SRAM器件包括：在单元阵列区域中具有至少一个单元有源区和外围电路区中的多个外围有源区，单元阵列区中的多个堆叠单元栅极图案和多个外围栅极的基板 设置在外围电路区域的外围有源区上的图案。 金属硅化物层设置在外围栅极图案的至少一部分上以及半导体衬底附近的外围栅极图案上，并且掩埋层图案设置在外围栅极图案和金属硅化物层的至少一部分上，并且 半导体衬底在周边栅极图案附近的部分。 蚀刻停止层和保护性层间绝缘层设置在周围栅极图案和电池阵列区域周围。 还公开了形成SRAM器件的方法。

    Methods of forming one transistor DRAM devices
    46.
    发明授权
    Methods of forming one transistor DRAM devices 有权
    形成一个晶体管DRAM器件的方法

    公开(公告)号：US08168530B2

    公开(公告)日：2012-05-01

    申请号：US12842703

    申请日：2010-07-23

    申请人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    发明人： Jae-Hun Jeong ,  Ki-Nam Kim ,  Soon-Moon Jung ,  Jae-Hoon Jang

    IPC分类号： H01L21/4763

    CPC分类号： H01L27/10802 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/108 ,  H01L27/10844 ,  H01L27/1203 ,  H01L29/7841

    摘要： A one transistor DRAM device includes: a substrate with an insulating layer, a first semiconductor layer provided on the insulating layer and including a first source region and a first region which are in contact with the insulating layer and a first floating body between the first source region and the first drain region, a first gate pattern to cover the first floating body, a first interlayer dielectric to cover the first gate pattern, a second semiconductor layer provided on the first interlayer dielectric and including a second source region and a second drain region which are in contact with the first interlayer dielectric and a second floating body between the second source region and the second drain region, and a second gate pattern to cover the second floating body.

    摘要翻译： 一个晶体管DRAM器件包括：具有绝缘层的衬底，设置在绝缘层上的第一半导体层，包括与绝缘层接触的第一源极区域和第一区域以及第一源极 区域和第一漏极区域，覆盖第一浮动体的第一栅极图案，覆盖第一栅极图案的第一层间电介质，设置在第一层间电介质上并包括第二源极区域和第二漏极区域的第二半导体层 其与第一层间电介质接触，第二浮动体与第二源极区和第二漏极区之间接触，第二栅极图案覆盖第二浮体。

    Non-volatile memory devices including etching protection layers and methods of forming the same
    48.
    发明授权
    Non-volatile memory devices including etching protection layers and methods of forming the same 有权
    包括蚀刻保护层的非易失性存储器件及其形成方法

    公开(公告)号：US07589375B2

    公开(公告)日：2009-09-15

    申请号：US11642297

    申请日：2006-12-20

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L27/115

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

    摘要翻译： 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。

    Non-volatile memory devices including etching protection layers and methods of forming the same
    50.
    发明申请
    Non-volatile memory devices including etching protection layers and methods of forming the same 有权
    包括蚀刻保护层的非易失性存储器件及其形成方法

    公开(公告)号：US20070096197A1

    公开(公告)日：2007-05-03

    申请号：US11642297

    申请日：2006-12-20

    申请人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    发明人： Jae-Hoon Jang ,  Soon-Moon Jung ,  Jong-Hyuk Kim ,  Young-Seop Rah ,  Han-Byung Park

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： H01L27/11 ,  H01L27/0688 ,  H01L27/105 ,  H01L27/1116

    摘要： A non-volatile memory device includes a semiconductor substrate including a cell array region and a peripheral circuit region. A first cell unit is on the semiconductor substrate in the cell array region, and a cell insulating layer is on the first cell unit. A first active body layer is in the cell insulating layer and over the first cell unit, and a second cell unit is on the first active body layer. The device further includes a peripheral transistor on the semiconductor substrate in the peripheral circuit region. The peripheral transistor has a gate pattern and source/drain regions, and a metal silicide layer is on the gate pattern and/or on the source/drain regions of the peripheral transistor. A peripheral insulating layer is on the metal silicide layer and the peripheral transistor, and an etching protection layer is between the cell insulating layer and the peripheral insulating layer and between the metal silicide layer and the peripheral insulating layer.

    摘要翻译： 非易失性存储器件包括包括单元阵列区域和外围电路区域的半导体衬底。 第一单元单元位于单元阵列区域中的半导体基板上，单元绝缘层位于第一单元单元上。 第一有源体层位于单元绝缘层中并在第一单元单元上，第二单元单元位于第一活性体层上。 该器件还包括在外围电路区域中的半导体衬底上的外围晶体管。 外围晶体管具有栅极图案和源极/漏极区域，并且金属硅化物层位于外围晶体管的栅极图案和/或源极/漏极区域上。 外围绝缘层位于金属硅化物层和外围晶体管上，蚀刻保护层位于电池绝缘层和外围绝缘层之间以及金属硅化物层和外围绝缘层之间。