公开(公告)号：US08489664B2

公开(公告)日：2013-07-16

申请号：US12399861

申请日：2009-03-06

Applicant: Viet Linh Do ,  Wei Fu ,  Arash Farhoodfar

Inventor： Viet Linh Do ,  Wei Fu ,  Arash Farhoodfar

IPC: G06F11/00

CPC classification number: G06F7/535 ,  G06F2207/5353

Abstract: A method is provided for first order accumulation in a single clock cycle. The method accepts a limited gain value and an accumulated value stored in a previous clock cycle. Using combinational logic, the limited gain value is summed with the accumulated value. If the summed value is between upper and lower limits, a non-weighted correction signal is supplied, and the summed value is the storage value. If the summed value is greater than the upper limit, a positive weighting is supplied, the (upper limit+1) is subtracted from the summed value, and the result is the storage value. If the summed value is less than the lower limit, then a negative weighting is supplied, the lower limit is subtracted from the summed value, and the result is the storage value. The storage value is loaded in memory for use as the accumulated value in the subsequent clock cycle.

Abstract translation: 提供了在单个时钟周期中用于一阶累积的方法。 该方法接受在前一个时钟周期中存储的有限增益值和累加值。 使用组合逻辑，将有限增益值与累积值相加。 如果总和值在上限和下限之间，则提供非加权校正信号，并且求和值为存储值。 如果总和值大于上限，则提供正加权，从求和值中减去（上限+ 1），结果为存储值。 如果总和值小于下限，则提供负加权，从求和值中减去下限，结果为存储值。 存储值被加载到存储器中以用作随后时钟周期中的累加值。

公开(公告)号：US08472514B2

公开(公告)日：2013-06-25

申请号：US12952178

申请日：2010-11-22

Applicant: Dariush Dabiri ,  Maged F. Barsoum

Inventor： Dariush Dabiri ,  Maged F. Barsoum

IPC: H03H7/30

CPC classification number: H03H21/0021 ,  H03H21/0012

Abstract: A circuit and method perform adaptive spectral enhancement at a frequency ω1 (also called “fundamental” frequency) on an input signal y which includes electromagnetic interference (EMI) at an unknown frequency, to generate a fundamental-enhanced signal φ1 (or its complement). The fundamental-enhanced signal φ1 (or complement) is thereafter used in a notching circuit (also called “fundamental notching” circuit) to generate a fundamental-notched signal y−φ1. The fundamental-notched signal y−φ1 is itself enhanced to generate a harmonic-enhanced signal φ2 that is used to notch the fundamental-notched signal y−φ1 again, in one or more additional notching circuits that are connected in series with the fundamental notching circuit. The result (“cascaded-harmonic-notched” signal) is relatively free of EMI noise (fundamental and harmonics), and is used as an error signal for an adaptation circuit that in turn identifies the fundamental frequency ω1. Use of a cascaded-harmonic-notched signal as the error signal improves speed of convergence of adaptation.

Abstract translation: 电路和方法在包括未知频率的电磁干扰（EMI）的输入信号y上以频率ω1（也称为“基本”频率）执行自适应频谱增强，以产生基本增强信号phi1（或其补码） 。 此后，在开槽电路（也称为“基本陷波”电路）中使用基本增强信号phi1（或补码）以产生基本缺陷信号y-phi1。 基本缺陷信号y-phi1本身被增强以产生用于在与基本开槽串联连接的一个或多个额外的开槽电路中再次陷波基波切割信号y-phi1的谐波增强信号phi2 电路。 结果（“级联谐波陷波”信号）相对没有EMI噪声（基波和谐波），并被用作自适应电路的误差信号，自适应电路又识别基频ω1。 使用级联谐波陷波信号作为误差信号提高适应性收敛速度。

公开(公告)号：US08438358B1

公开(公告)日：2013-05-07

申请号：US12729210

申请日：2010-03-22

Applicant: Waseem Saify Kraipak ,  George Bendak

Inventor： Waseem Saify Kraipak ,  George Bendak

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F11/00 ,  G11C29/00 ,  G11C7/04 ,  G11C11/34 ,  H01L35/00 ,  H01L37/00 ,  G06F1/00 ,  G06F1/32

CPC classification number: G11C7/04 ,  G06F1/206 ,  G06F1/3225 ,  G06F1/3275 ,  G11C11/40615 ,  G11C11/40626 ,  G11C29/56 ,  G11C2029/0401 ,  G11C2207/2254 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/16

Abstract: A system and method are provided for using a system-on-chip (SoC) memory speed control logic core to control memory maintenance and access parameters. A SoC is provided with an internal hardware-enabled memory speed control logic (MSCL) core. An array of SoC memory control parameter registers is accessed and a set of parameters is selected from one of the registers. The selected set of parameters is delivered to a SoC memory controller, to replace an initial set of parameters, and the memory controller manages an off-SoC memory using the delivered set of parameters.

Abstract translation: 提供了一种使用片上系统（SoC）存储器速度控制逻辑核来控制存储器维护和访问参数的系统和方法。 SoC提供了内部硬件使能内存速度控制逻辑（MSCL）内核。 访问一组SoC存储器控制参数寄存器，并从其中一个寄存器中选择一组参数。 所选择的一组参数被传递给SoC存储器控制器，以替换初始参数集，并且存储器控制器使用传递的参数集管理Off-SoC存储器。

公开(公告)号：US08429315B1

公开(公告)日：2013-04-23

申请号：US13167783

申请日：2011-06-24

Applicant: Keyur Chudgar ,  Satish Sathe

Inventor： Keyur Chudgar ,  Satish Sathe

IPC: G06F3/00 ,  G06F13/14

CPC classification number: H04L12/40143 ,  H04L12/413 ,  H04L47/50 ,  H04L49/102 ,  H04L49/109 ,  H04L49/351 ,  H04L49/90

Abstract: In a system-on-chip (SoC) including a processor, a method is provided for stashing packet information that prevents cache thrashing. In operation, an Ethernet subsystem accepts a plurality of packets and sends the packets to an external memory for storage. A packet descriptor is derived for each accepted packet and is added to an ingress queue. Packet descriptors are transferred from the ingress queue to an egress queue supplying the packet descriptors to a processor. A context manager monitors the fill level of packet descriptors in the egress queue. In response to monitoring the fill level, the context manager stashes packets from the external memory into a cache, where each stashed packet is associated with a packet descriptor in the egress queue. Packet descriptors are transferred from the ingress queue to the egress queue in response to a number of packet descriptors in the egress queue falling below the fill level.

Abstract translation: 在包括处理器的片上系统（SoC）中，提供了一种用于冻结分组信息以防止高速缓存颠簸的方法。 在操作中，以太网子系统接受多个分组并将分组发送到外部存储器用于存储。 为每个接受的包导出包描述符，并将其添加到入口队列。 分组描述符从入口队列传送到向处理器提供分组描述符的出口队列。 上下文管理器监视出口队列中的分组描述符的填充级别。 响应于监视填充级别，上下文管理器将来自外部存储器的数据包存储到高速缓存中，其中每个被封闭的分组与出口队列中的分组描述符相关联。 响应于出口队列中的多个分组描述符落入填充级别以下，分组描述符从入口队列传送到出口队列。

公开(公告)号：US08397197B1

公开(公告)日：2013-03-12

申请号：US13115858

申请日：2011-05-25

Applicant: Mitrajit Chatterjee ,  Sandeep Badida

Inventor： Mitrajit Chatterjee ,  Sandeep Badida

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/84

Abstract: A circuit analysis tool is provided, enabled as computer software instructions, for budgeting time delays between integrated circuit (IC) modules. The instructions accept a command enabling an IC floor-plan including a first module and a second module. The first module includes a first circuit element having a signal output interface, and an output port. The second module includes an input port, and a second circuit element having a signal input interface. A command is accepted defining a maximum delay value, and a first delay value is estimated between the first circuit element signal output interface and the first module output port. A second delay value is estimated between the second circuit element signal input interface and the second module input port, and a third delay value is estimated between the first module output port and the second module input port. The first, second, and third delay values are summed, creating a time budget estimate. The time budget estimate is approved if it is less than the maximum delay value.

Abstract translation: 提供电路分析工具，作为计算机软件指令，用于对集成电路（IC）模块之间的时间延迟进行预算。 指令接受启用包括第一模块和第二模块的IC平面图的命令。 第一模块包括具有信号输出接口的第一电路元件和输出端口。 第二模块包括输入端口和具有信号输入接口的第二电路元件。 接受定义最大延迟值的命令，并且在第一电路元件信号输出接口和第一模块输出端口之间估计第一延迟值。 在第二电路元件信号输入接口和第二模块输入端口之间估计第二延迟值，并且在第一模块输出端口和第二模块输入端口之间估计第三延迟值。 将第一，第二和第三延迟值相加，创建时间预算估计。 如果小于最大延迟值，则批准时间预算估算值。

公开(公告)号：US08391349B1

公开(公告)日：2013-03-05

申请号：US12617610

申请日：2009-11-12

Applicant: Alireza Khalili

Inventor： Alireza Khalili

IPC: H03H7/30

CPC classification number: H04B3/04 ,  H04L25/03878

Abstract: A combination equalizer and automatic gain control (AGC) is provided for high-speed receivers. The combination circuit comprises a first AGC having an input to accept a communication signal and an input to accept a first control signal. The first AGC modifies the communication signal gain in response to the first control signal, to supply a first stage signal at an output. An equalizer has an input to accept the first stage signal and an input to accept a second control signal. The equalizer modifies the frequency characteristics of the first stage signal in response to the second control signal, to supply an equalized signal at an output. A second AGC has an input to accept the equalized signal and an input to accept a third control signal. The second AGC modifies the equalized signal gain in response to the third control signal, to supply a second stage signal at an output.

Abstract translation: 为高速接收机提供组合均衡器和自动增益控制（AGC）。 组合电路包括具有接收通信信号的输入的第一AGC和用于接受第一控制信号的输入。 第一AGC响应于第一控制信号来修改通信信号增益，以在输出端提供第一级信号。 均衡器具有接收第一级信号的输入端和用于接受第二控制信号的输入端。 均衡器响应于第二控制信号修改第一级信号的频率特性，以在输出端提供均衡的信号。 第二AGC具有接受均衡信号的输入端和用于接受第三控制信号的输入端。 第二AGC响应于第三控制信号来修改均衡的信号增益，以在输出端提供第二级信号。

公开(公告)号：US08347169B1

公开(公告)日：2013-01-01

申请号：US12714741

申请日：2010-03-01

Applicant: Omer Acikel

Inventor： Omer Acikel

IPC: H03M13/00

CPC classification number: H03M13/611 ,  H03M13/1102 ,  H03M13/6502

Abstract: A system and method are provided for creating codewords using common partial parity products. The method initially accepts an algorithm for creating p indexed parity bit positions, where the parity bit for each position is calculated from mathematical operations performed on bits from n indexed user word positions. A first group of parity bit positions is found, where the parity bit for each position in the first group is calculated using at least a first number of common mathematical operations. A second group of parity bit positions is found, where the parity bit for each position in the second group is calculated using at least a second number of common mathematical operations. The common mathematical operations are subtracted from the first and second group of parity bit position calculations, so that unique mathematical operations can be found, associated with each parity bit position calculation in the first and second group.

Abstract translation: 提供了一种使用公共部分奇偶校验产生来创建码字的系统和方法。 该方法最初接受用于创建p个索引的奇偶校验位位置的算法，其中通过对来自n个索引用户字位置的比特执行的数学运算来计算每个位置的奇偶校验位。 找到第一组奇偶校验位位置，其中使用至少第一数量的公共数学运算来计算第一组中每个位置的奇偶校验位。 找到第二组奇偶校验位位置，其中使用至少第二数量的公共数学运算来计算第二组中每个位置的奇偶校验位。 从第一组和第二组奇偶校验位位置计算中减去常见的数学运算，从而可以找到与第一组和第二组中的每个奇偶校验位位置计算相关联的唯一数学运算。

公开(公告)号：US08268669B2

公开(公告)日：2012-09-18

申请号：US13050822

申请日：2011-03-17

Applicant: Joseph Martin Patterson

Inventor： Joseph Martin Patterson

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L23/544 ,  G01R31/2853 ,  G01R31/308 ,  H01L22/14 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/54433 ,  H01L2223/5448 ,  H01L2223/54486 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A method is provided for detecting laser optical paths in integrated circuit (IC) packages. The method provides an IC die encapsulated as a package in a compound of glass spheres and epoxy. Power is supplied to the IC. The IC is scanned with a laser. Typically, a laser wavelength is used that is minimally absorbed by the glass spheres in the epoxy compound of the IC package, and changes in current to the IC are detected. A detected current change is cross-referenced against a scanned IC package surface region. This process identifies an optical pathway underlying the scanned IC package surface region. In some aspects, this process leads to the identification of a glass sphere-collecting package structure underlying the optical pathway. Examples of a glass sphere-collecting structure might include an inner lead wire, lead frame edge, or die edge.

Abstract translation: 提供了一种用于在集成电路（IC）封装中检测激光光路的方法。 该方法提供封装在玻璃球和环氧树脂化合物中的IC封装。 电源供给IC。 IC用激光扫描。 通常，使用由IC封装的环氧化合物中的玻璃球最少吸收的激光波长，并且检测到对IC的电流的变化。 检测到的电流变化与扫描的IC封装表面区域相互参照。 该过程识别扫描的IC封装表面区域下面的光学路径。 在一些方面，该过程导致了在光学路径下面的玻璃球收集包装结构的识别。 玻璃球收集结构的实例可以包括内部引线，引线框架边缘或管芯边缘。

公开(公告)号：US08264388B1

公开(公告)日：2012-09-11

申请号：US12899500

申请日：2010-10-06

Applicant: Hanan Cohen ,  Simon Pang

Inventor： Hanan Cohen ,  Simon Pang

IPC: H03M1/48

CPC classification number: H03L7/081 ,  H03L7/093 ,  H03L2207/50

Abstract: A digital phase-locked loop (DPLL), a supporting digital frequency integrator, and a method are provided for deriving a digital phase error signal in a DPLL. A digital frequency integrator periodically accepts a digital tdcOUT message from a Time-to-Digital Converter (TDC) representing a measured ratio of a reference clock (Tref) period to a synthesizer clock (Tdco) period. Also accepted is a digital message selecting a first ratio (Nf). In response, a digital phase error (pherr) message is periodically supplied that is proportional to an error in phase between the reference clock and the (synthesizer clock*Nf).

Abstract translation: 提供数字锁相环（DPLL），支持数字频率积分器和方法，用于导出DPLL中的数字相位误差信号。 数字频率积分器周期性地接收来自表示参考时钟（Tref）周期与合成器时钟（Tdco）周期的测量比率的时间数字转换器（TDC））的数字tdcOUT消息。 也接受选择第一比率（Nf）的数字消息。 作为响应，周期性地提供与参考时钟和（合成器时钟* Nf）之间的相位误差成比例的数字相位误差（pherr）消息。

公开(公告)号：US08248106B1

公开(公告)日：2012-08-21

申请号：US12949427

申请日：2010-11-18

Applicant: Hanan Cohen ,  Simon Pang

Inventor： Hanan Cohen ,  Simon Pang

IPC: G01R23/02

CPC classification number: H03L7/081 ,  H03L7/095 ,  H03L7/16

Abstract: A system and method are provided for frequency lock detection using a digital phase error. A lock detection module accepts a digital phase error (pherr) message proportional to an error in phase between a reference clock and a (synthesizer clock*Nf). Also accepted is a unitless frequency error tolerance value (Δf). The lock detection module periodically supplies a lock detect signal, indicating whether the synthesizer clock frequency is within the frequency error tolerance value of the reference clock frequency.

Abstract translation: 提供了一种使用数字相位误差进行频率锁定检测的系统和方法。 锁定检测模块接受与参考时钟和（合成器时钟* Nf）之间的相位误差成比例的数字相位误差（pherr）消息。 也接受无单位频率容差值（＆Dgr; f）。 锁定检测模块周期性地提供锁定检测信号，指示合成器时钟频率是否在参考时钟频率的频率容差值内。