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    TRANSISTOR STRUCTURES WITH INTERLEAVED BODY CONTACTS AND GATE CONTACTS
    41.
    发明公开
    TRANSISTOR STRUCTURES WITH INTERLEAVED BODY CONTACTS AND GATE CONTACTS 审中-公开

    公开(公告)号：US20240243175A1

    公开(公告)日：2024-07-18

    申请号：US18098188

    申请日：2023-01-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkata Narayana Rao Vanukuru ,  Steven M. Shank

    IPC: H01L29/10 ,  H01L21/74 ,  H01L27/12

    CPC classification number: H01L29/1087 ,  H01L21/743 ,  H01L27/1203

    Abstract: Structures including a field-effect transistor field-effect and methods of forming a structure including a field-effect transistor. The structure comprises a trench isolation region in a substrate, and a body contact region that extends through the trench isolation region to the substrate. The structure further comprises a field-effect transistor including a gate connector, a first gate finger that extends from the gate connector, a second gate finger that extends from the gate connector, and a source/drain region disposed between the first gate finger and the second gate finger. The gate connector is positioned over the trench isolation region. The structure further comprises a gate contact coupled to the gate connector, and a body contact that penetrates through a portion of the gate connector to the body contact region.

    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS
    45.
    发明公开
    THRESHOLD VOLTAGE-PROGRAMMABLE FIELD EFFECT TRANSISTOR-BASED MEMORY CELLS AND LOOK-UP TABLE IMPLEMENTED USING THE MEMORY CELLS 审中-公开

    公开(公告)号：US20240221810A1

    公开(公告)日：2024-07-04

    申请号：US18607725

    申请日：2024-03-18

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Venkatesh P. Gopinath ,  Pirooz Parvarandeh

    IPC: G11C11/22

    CPC classification number: G11C11/223 ,  G11C11/2273 ,  G11C11/2275

    Abstract: Disclosed is threshold voltage (VT)-programmable field effect transistor (FET)-based memory cell including a first transistor and a second transistor (which has an electric-field based programmable VT) connected in series between two voltage source lines. The gates of the transistors are connected to different wordlines and a sense node is at the junction between the two transistors. In preferred embodiments, the first transistor is a PFET and the second transistor is an NFET. Different operating modes (e.g., write 0 or 1 and read) are achieved using specific combinations of voltage pulses on the wordlines and voltage source lines. The memory cell is non-volatile, exhibits relatively low leakage, and has a relatively small footprint as compared to a conventional memory cell. Also disclosed are a look-up table (LUT) incorporating multiple threshold voltage (VT)-programmable field effect transistor (FET)-based memory cells and associated methods.

    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER
    49.
    发明公开
    INPUT BUFFER WITH HYSTERESIS-INTEGRATED VOLTAGE PROTECTION DEVICES AND RECEIVER INCORPORATING THE INPUT BUFFER 审中-公开

    公开(公告)号：US20240195416A1

    公开(公告)日：2024-06-13

    申请号：US18064978

    申请日：2022-12-13

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Dzung T. Tran ,  Deepti A. Pant ,  Shibly S. Ahmed

    IPC: H03K19/003

    CPC classification number: H03K19/00361 ,  H03K19/00315

    Abstract: Disclosed is an input buffer with hysteresis-integrated voltage protection devices for avoiding violations of maximum gate-to-source voltage limitations when the maximum input voltage is greater than the maximum gate-to-source voltage limitation. The input buffer includes a chain of transistors including two P-channel FETs (PFETs) and two N-channel FETs (NFETs). The data input to the input buffer controls the gates of the transistors in the chain so the data output from the input buffer at the junction between the PFETs and NFETs is inverted. The input buffer also includes a hysteresis feedback loop to prevent noise-induced switching of the output. The hysteresis feedback loop also includes voltage protection devices integrated therein to avoid maximum gate-to-source violations when the loop results in a hysteresis voltage being fed back into the chain at the source region of a transistor in the chain. Also disclosed is a receiver incorporating the input buffer.

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