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41.发明授权公开(公告)号：US12250818B2
公开(公告)日：2025-03-11
申请号：US17586682
申请日：2022-01-27
Applicant: Micron Technology, Inc.
Inventor： Pei Qiong Cheung , Zhixin Xu , Yuan Fang
Abstract: Some embodiments include a method of forming an assembly. A first stack of alternating first and second tiers is formed over a conductive structure. A first opening is formed to extend through the first stack. A sidewall of the first opening is lined with a first liner material. The first liner material is converted to a first charge-blocking material. Sacrificial material is formed within the first opening. A second stack of alternating third and fourth tiers is formed over the first stack. A second opening is formed to extend through the second stack to the sacrificial material. A second liner material is formed within the second opening, is anisotropically etched, and is then converted to a second charge-blocking material. The sacrificial material is removed. Charge-storage material, dielectric material and channel material are formed adjacent to the charge-blocking material. Some embodiments include integrated assemblies.
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公开(公告)号：US12250812B2
公开(公告)日：2025-03-11
申请号：US18094906
申请日：2023-01-09
Applicant: Micron Technology, Inc.
Inventor： Jordan D. Greenlee , Nancy M. Lomeli , John D. Hopkins , Jiewei Chen , Indra V. Chary , Jun Fang , Vladimir Samara , Kaiming Luo , Rita J. Klein , Xiao Li , Vinayak Shamanna
Abstract: Some embodiments include an integrated assembly having a source structure, and having a stack of alternating conductive levels and insulative levels over the source structure. Cell-material-pillars pass through the stack. The cell-material-pillars are arranged within a configuration which includes a first memory-block-region and a second memory-block-region. The cell-material-pillars include channel material which is electrically coupled with the source structure. Memory cells are along the conductive levels and include regions of the cell-material-pillars. A panel is between the first and second memory-block-regions. The panel has a first material configured as a container shape. The container shape defines opposing sides and a bottom of a cavity. The panel has a second material within the cavity. The second material is compositionally different from the first material. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US12250499B2
公开(公告)日：2025-03-11
申请号：US17806888
申请日：2022-06-14
Applicant: Micron Technology, Inc.
Inventor： Alyssa Scarbrough , John Hopkins , Zahra Hosseinimakarem , Yi Hu
Abstract: In some implementations, a device may receive, from a sensor of a vehicle, sensor data. The device may detect whether an event causing damage to the vehicle has occurred or is expected to occur based on the sensor data being greater than a threshold, wherein the threshold is based on an on-off status of the vehicle and a sensor type. The device may activate, based on whether the event has occurred or is expected to occur, a camera of the vehicle to capture video data of a scene associated with the vehicle. The device may transmit, to a server, an indication that indicates the event and the video data.
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公开(公告)号：US12249362B2
公开(公告)日：2025-03-11
申请号：US18120133
申请日：2023-03-10
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Efrem Bolandrina
Abstract: Methods, systems, and devices for a single plate configuration and memory array operation are described. A non-volatile memory array may utilize a single plate to cover a subset of the array. One or more memory cells of the subset may be selected by operating the plate and an access line of an unselected memory cell at a fixed voltage. A second voltage may be applied to an access line of the selected cell, and subsequently reduced to perform an access operation. Removing the applied voltage may allow for the memory cell to undergo a recovery period prior to a subsequent access operation.
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公开(公告)号：US12248705B2
公开(公告)日：2025-03-11
申请号：US17865760
申请日：2022-07-15
Applicant: Micron Technology, Inc.
Inventor： Giuseppe Cariello , Jonathan Scott Parry
Abstract: Systems and methods of memory operation involving dynamic adjustment of write policy based on performance needs are disclosed. In one embodiment, an exemplary method may comprise monitoring memory performance parameters related to a programming operation being scheduled, selecting a write policy based on the memory performance parameters monitored, executing a memory control process that is configured to switch between the first addressing scheme and the second addressing scheme, and programming a first superpage of the programming operation using the first addressing scheme and programing a second superpage of the programming operation using the second addressing scheme.
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Patent Agency Ranking
46.发明申请公开(公告)号：US20250079371A1
公开(公告)日：2025-03-06
申请号：US18954176
申请日：2024-11-20
Applicant: Micron Technology, Inc.
Inventor： Christopher Glancey , Shams U. Arifeen , Koustav Sinha , Quang Nguyen
IPC: H01L23/00
Abstract: Semiconductor die assemblies with flexible interconnects, and associated methods and systems are disclosed. The semiconductor die assembly includes a package substrate and a semiconductor die attached to the package substrate through the flexible interconnects. The flexible interconnects include one or more rigid sections and one or more flexible sections, each of which is disposed next to the rigid sections. The flexible sections may include malleable materials with relatively low melting temperatures (e.g., having relatively low modulus at elevated temperatures) such that the flexible interconnects can have reduced flexural stiffness during the assembly process. The malleable materials of the flexible interconnects, through plastic deformation in response to stress generated during the assembly process, may facilitate portions of the flexible interconnects to shift so as to reduce transfer of the stress to other parts of the semiconductor die assembly-e.g., circuitry of the semiconductor die.
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公开(公告)号：US20250078948A1
公开(公告)日：2025-03-06
申请号：US18952806
申请日：2024-11-19
Applicant: Micron Technology, Inc.
Inventor： Kai Wang
Abstract: Methods, systems, and devices for techniques for initializing memory error correction are described. A memory system may perform operations relating to writing data to multiple memory cells belonging to one or more rows of the memory system in response to a single write command. For example, the memory system may receive (e.g., from a host system) an activation command (e.g., a row group activation command) indicating a row group address. The memory system may activate a set of rows indicated by the row group address. In response to a write command (e.g., a row group write command), the memory system may write data in a respective memory cell of each row indicated by the row group address. For example, each memory cell to be written may correspond to a column address included in the write command. The memory system may write a same logic state to each memory cell.
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公开(公告)号：US20250078902A1
公开(公告)日：2025-03-06
申请号：US18789682
申请日：2024-07-31
Applicant: Micron Technology, Inc.
Inventor： Sangjin Byeon
IPC: G11C11/4074 , G11C5/14 , G11C11/4076
Abstract: A method to attenuate excessive supply voltage fluctuations in a memory system comprising a memory controller and a memory device configured to store and retrieve data is provided. The method includes detecting a potential supply voltage fluctuation at a voltage-threshold violation detection circuit in the memory controller, wherein the potential supply voltage fluctuation corresponds to an inrushing current from an initialization state or a surge of current from a switch to a busy state after staying in a long-term idle state. In response to detecting the potential supply voltage fluctuation, the method includes generating a control signal from the voltage-threshold violation detection circuit. The method includes transmitting the control signal from the memory controller to the memory device. The method includes decoding the control signal in the memory device. The method includes attenuating the potential supply voltage fluctuation to prepare for memory access.
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公开(公告)号：US20250077411A1
公开(公告)日：2025-03-06
申请号：US18954112
申请日：2024-11-20
Applicant: Micron Technology, Inc.
Inventor： David A. Roberts
IPC: G06F12/02 , G06F12/0882 , G06F13/16
Abstract: Systems, apparatuses, and methods related to memory access statistics monitoring are described. A host is configured to map pages of memory for applications to a number of memory devices coupled thereto. A first memory device comprises a monitoring component configured to monitor access statistics of pages of memory mapped to the first memory device. A second memory device does not include a monitoring component capable of monitoring access statistics of pages of memory mapped thereto. The host is configured to map a portion of pages of memory for an application to the first memory device in order to obtain access statistics corresponding to the portion of pages of memory upon execution of the application despite there being space available on the second memory device and adjust mappings of the pages of memory for the application based on the obtained access statistics corresponding to the portion of pages.
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公开(公告)号：US20250077369A1
公开(公告)日：2025-03-06
申请号：US18750144
申请日：2024-06-21
Applicant: Micron Technology, Inc.
Inventor： Craig William Warner , Tony M. Brewer
Abstract: Disclosed in some examples are methods, systems, devices, and architectures which provide for techniques for memory device and memory fabric redundancy within distributed memory systems. In some examples, two memory devices are paired and each stores a same set of data such that writes to the memory devices are duplicated and reads may be satisfied from either device. In some examples, a memory processing unit (MPU) may be incorporated into the memory architecture to support these paired memory devices. The MPU may be placed between the host and a multi-planed memory fabric which connects to multi-ported CXL memory devices. In some examples, the MPU may also enable the use of alternative fabric links. That is, if a memory fabric link between the MPU and a memory device is unavailable, an alternative link may be utilized to restore connectivity to a memory device.
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