公开(公告)号：US5500811A

公开(公告)日：1996-03-19

申请号：US377096

申请日：1995-01-23

申请人： Alan G. Corry

发明人： Alan G. Corry

IPC分类号： H03H17/02 ,  H03H17/06 ,  G06F15/31 ,  G06F7/38

CPC分类号： H03H17/0275 ,  H03H17/06

摘要： A compact Finite Impulse Response (FIR) filter using one or both of a compact address sequencer and a compact multiplier/accumulator. The address sequencer exploits certain symmetry properties existing between different phases of a polyphase FIR filter in order to reduce coefficient storage and simplify address sequencing. The multiplier/accumulator is capable of performing two multiply/accumulate operations per clock cycle, avoiding in certain instances the need to add a second multiplier/accumulator. The area required to realize a FIR filter for performing real-time filter is therefore reduced.

摘要翻译： 使用紧凑型地址排序器和紧凑型乘法器/累加器之一或两者的紧凑型有限脉冲响应（FIR）滤波器。 地址序列器利用多相FIR滤波器的不同相之间存在的某些对称性，以减少系数存储并简化地址排序。 乘法器/累加器能够在每个时钟周期执行两次乘法/累加操作，避免在某些情况下需要添加第二个乘法器/累加器。 因此，实现用于执行实时滤波器的FIR滤波器所需的面积减少。

公开(公告)号：US5386140A

公开(公告)日：1995-01-31

申请号：US114980

申请日：1993-08-31

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/70

CPC分类号： H01L29/66272 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/732 ,  Y10S148/01

摘要： A bipolar transistor having an emitter, a base, and a collector includes an intrinsic base region having narrow side areas and a wider central area. The side areas are located adjacent to the extrinsic base region, while the central area is disposed underneath the emitter. The lateral doping profile of the base is tailored so that the doping concentrations in the extrinsic region and the central area are relatively high compared to the doping concentration of the narrow side areas of the intrinsic base. The combination of the narrow side areas and the lateral base doping profile constrains the depletion region within the base thereby lowering punch-through voltage of the transistor without loss of beta.

摘要翻译： 具有发射极，基极和集电极的双极晶体管包括具有窄侧面区域和较宽中心区域的本征基极区域。 侧面区域位于外部基极区域附近，而中央区域设置在发射体下方。 定制基极的横向掺杂分布，使得与本征基极的窄边区域的掺杂浓度相比，外在区域和中心区域中的掺杂浓度相对较高。 窄边区域和横向基极掺杂曲线的组合限制了基极内的耗尽区域，从而降低晶体管的穿通电压而不损失β。

公开(公告)号：US5232047A

公开(公告)日：1993-08-03

申请号：US820365

申请日：1992-01-14

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： F28F3/12 ,  H01L23/473

CPC分类号： F28F3/12 ,  H01L23/473 ,  F28F2260/02 ,  H01L2924/0002

摘要： A microscopic laminar-flow heat exchanger, well-suited for cooling a heat generating device such as a semiconductor integrated circuit, includes a plurality of thin plates, laminated together to form a block. Each plate has a microscopic recessed portion etched into one face of the plate and a pair of holes cut through the plate such that when the block is formed, the holes align to form a pair of coolant distribution manifolds. The manifolds are connected via the plurality of microscopic channels formed from the recessed portions during the lamination process. Coolant flow through these channels effectuates heat removal.

摘要翻译： 适用于冷却诸如半导体集成电路的发热装置的微型层流式热交换器包括多个薄板，层压在一起以形成块体。 每个板具有蚀刻到板的一个面中的微观凹陷部分和穿过板切割的一对孔，使得当形成块时，孔对准以形成一对冷却剂分配歧管。 在层压过程中，歧管通过由凹部形成的多个微细通道相连接。 通过这些通道的冷却液流动可实现除热。

公开(公告)号：US5108945A

公开(公告)日：1992-04-28

申请号：US647709

申请日：1991-01-28

申请人： James A. Matthews

发明人： James A. Matthews

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/417

CPC分类号： H01L21/28211 ,  H01L21/28525 ,  H01L21/7688 ,  H01L21/76897 ,  H01L21/8249 ,  H01L29/41708 ,  H01L29/41775 ,  H01L2924/0002 ,  Y10S148/019 ,  Y10S148/136

摘要： A process for faricating polysilicon resistors and polysilicon interconnects coupled to MOS field-effect devices in a silicon substrate includes the steps of depositing and etching a first polysilicon layer to form the gates of the MOS devices; then depositing a second layer of polysilicon between the gates. The second polysilicon layer is then etched so that its upper surface is substantially coplanar with the gates. Contact openings are then defined to the source, drain and gate members of the devices through an insulative layer formed over the first and second polysilicon layers. Next, a metal layer is deposited to fill the openings and is patterned to define electrical contacts to the devices. The patterning step also defines the interconnect lines in the metal layer. A third polysilicon layer is then deposited and patterned to define the polysilicon resistors and interconnects.

摘要翻译： 耦合到硅衬底中的MOS场效应器件的多晶硅电阻器和多晶硅互连件的处理过程包括沉积和蚀刻第一多晶硅层以形成MOS器件的栅极的步骤; 然后在所述栅极之间沉积第二层多晶硅。 然后蚀刻第二多晶硅层，使得其上表面与栅极基本上共面。 然后通过形成在第一和第二多晶硅层上的绝缘层将接触开口限定到器件的源极，漏极和栅极部件。 接下来，沉积金属层以填充开口并被图案化以限定到器件的电触点。 图案化步骤还限定了金属层中的互连线。 然后沉积和图案化第三多晶硅层以限定多晶硅电阻器和互连。

公开(公告)号：US08812821B2

公开(公告)日：2014-08-19

申请号：US13584235

申请日：2012-08-13

申请人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

发明人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC分类号： G06F9/30

CPC分类号： G06F9/30014 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3885 ,  G06F12/0886

摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

摘要翻译： 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

公开(公告)号：US08769248B2

公开(公告)日：2014-07-01

申请号：US13493738

申请日：2012-06-11

申请人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

发明人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC分类号： G06F9/302

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

摘要： Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

公开(公告)号：US08683182B2

公开(公告)日：2014-03-25

申请号：US13493750

申请日：2012-06-11

申请人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

发明人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC分类号： G06F9/302

CPC分类号： G06F9/30014 ,  G06F9/30018 ,  G06F9/30025 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30087 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3012 ,  G06F9/30123 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/3816 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3873 ,  G06F9/3885 ,  G06F15/7832

摘要： Systems and apparatuses are presented relating a programmable processor comprising an execution unit that is operable to decode and execute instructions received from an instruction path and partition data stored in registers in the register file into multiple data elements, the execution unit capable of executing group data handling operations that re-arrange data elements in different ways in response to data handling instructions, the execution unit further capable of executing a plurality of different group floating-point and group integer arithmetic operations that each arithmetically operates on the multiple data elements stored in registers in the register file to produce a catenated result that is returned to a register in the register file, wherein the catenated result comprises a plurality of individual results.

摘要翻译： 提出了一种可编程处理器的系统和装置，其包括执行单元，该执行单元可操作以解码和执行从指令路径接收的指令，并将存储在寄存器堆中的寄存器中的数据分割成多个数据元素，该执行单元能够执行群组数据处理 响应于数据处理指令以不同方式重新布置数据元素的操作，所述执行单元还能够执行多个不同的组浮点和组整数运算，每个算术运算对存储在寄存器中的多个数据元素进行算术运算 该寄存器文件产生一个返回到该寄存器文件中的一个寄存器的连线结果，其中该连接结果包括多个单独的结果。

公开(公告)号：US08289335B2

公开(公告)日：2012-10-16

申请号：US11346213

申请日：2006-02-03

申请人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

发明人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC分类号： G06T1/00 ,  G06T15/00 ,  G06F15/00 ,  G06F7/38

CPC分类号： G06F9/3001 ,  G03F1/36 ,  G06F9/30 ,  G06F9/30007 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/3004 ,  G06F9/30043 ,  G06F9/30054 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/35 ,  G06F9/383 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3885 ,  G06F9/4484 ,  G06F9/45533 ,  G06F12/02 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/12 ,  H03M13/158 ,  H03M13/4169 ,  Y02D10/13 ,  Y02D10/26 ,  Y02D10/28 ,  Y02P90/265

摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

摘要翻译： 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。

公开(公告)号：US20120215826A1

公开(公告)日：2012-08-23

申请号：US13462648

申请日：2012-05-02

申请人： Craig Hansen ,  Bruce Bateman ,  John Moussouris

发明人： Craig Hansen ,  Bruce Bateman ,  John Moussouris

IPC分类号： G06F7/487 ,  G06F7/485

CPC分类号： G06F7/5338 ,  G06F7/4812 ,  G06F7/49994 ,  G06F7/57 ,  G06F7/724 ,  G06F9/30014 ,  G06F9/30036 ,  G06F17/15 ,  G06F17/16 ,  G06F2207/3812 ,  G06F2207/382 ,  G06F2207/3824 ,  G06F2207/3828

摘要： The present invention provides a system and method for improving the performance of general-purpose processors by implementing a functional unit that computes the product of a matrix operand with a vector operand, producing a vector result. The functional unit fully utilizes the entire resources of a 128b by 128b multiplier regardless of the operand size, as the number of elements of the matrix and vector operands increase as operand size is reduced. The unit performs both fixed-point and floating-point multiplications and additions with the highest-possible intermediate accuracy with modest resources.

摘要翻译： 本发明提供了一种用于通过实现一个功能单元来提高通用处理器的性能的系统和方法，所述功能单元使用向量操作数来计算矩阵操作数的乘积，产生向量结果。 功能单元完全利用128b乘128b乘法器的全部资源，无论操作数大小如何，因为矩阵和向量操作数的元素数量随着操作数大小的减小而增加。 该单元通过适度的资源执行具有最高可能的中间精度的定点和浮点乘法和补充。

公开(公告)号：US20120117441A1

公开(公告)日：2012-05-10

申请号：US13354214

申请日：2012-01-19

申请人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

发明人： Craig Hansen ,  John Moussouris ,  Alexia Massalin

IPC分类号： G06F9/302 ,  G06F11/10 ,  G06F9/305 ,  H03M13/05 ,  G06F9/312 ,  G06F9/345

CPC分类号： G06F9/30014 ,  G06F9/30007 ,  G06F9/30021 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/30167 ,  G06F9/32 ,  G06F9/34 ,  G06F9/3824 ,  G06F9/383 ,  G06F9/3885 ,  G06F12/0886

摘要： A programmable processor and method for improving the performance of processors by expanding at least two source operands, or a source and a result operand, to a width greater than the width of either the general purpose register or the data path width. The present invention provides operands which are substantially larger than the data path width of the processor by using the contents of a general purpose register to specify a memory address at which a plurality of data path widths of data can be read or written, as well as the size and shape of the operand. In addition, several instructions and apparatus for implementing these instructions are described which obtain performance advantages if the operands are not limited to the width and accessible number of general purpose registers.

摘要翻译： 一种可编程处理器和方法，用于通过将至少两个源操作数或源和结果操作数扩展到大于通用寄存器或数据路径宽度的宽度的宽度来提高处理器的性能。 本发明通过使用通用寄存器的内容来指定可以读取或写入数据的多个数据路径宽度的存储器地址，并且基本上大于处理器的数据路径宽度的操作数，以及 操作数的大小和形状。 此外，描述了用于实现这些指令的几个指令和装置，其如果操作数不限于通用寄存器的宽度和可访问数量，则获得性能优点。