公开(公告)号：US4167806A

公开(公告)日：1979-09-18

申请号：US835776

申请日：1977-09-22

Applicant: Pierre Kumurdjian

Inventor： Pierre Kumurdjian

IPC: H01L45/00 ,  B01J17/00

CPC classification number: H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/1625 ,  H01L45/1675 ,  Y10S438/90

Abstract: An active zone between a lower electrode deposited on a substrate and an upper electrode constitutes a portion of an amorphous semiconducting layer and is defined either by the dimensions of the upper electrode or by a window formed in an insulating layer. The method of fabrication consists in forming the two electrodes and the two active and insulating layers, the active layer and insulating layer being fabricated from amorphous compounds which are constituted either wholly or in part by the same elements.

Abstract translation: 沉积在基板上的下电极和上电极之间的有源区域构成非晶半导体层的一部分，并且由上电极的尺寸或由绝缘层形成的窗口来限定。 制造方法在于形成两个电极和两个有源绝缘层和绝缘层，有源层和绝缘层由全部或部分由相同元件构成的无定形化合物制成。

公开(公告)号：US4166574A

公开(公告)日：1979-09-04

申请号：US911234

申请日：1978-05-31

Applicant: Masanori Yokoyama

Inventor： Masanori Yokoyama

IPC: B28D5/00 ,  B28D5/04 ,  G06K1/12 ,  H01L23/544 ,  G06K17/00 ,  B01J17/00 ,  G06K19/06 ,  G06K7/14

CPC classification number: G06K1/12 ,  B28D5/00 ,  B28D5/047 ,  H01L23/544 ,  H01L2223/54493 ,  H01L2924/0002 ,  Y10S235/901 ,  Y10T29/41

Abstract: An apparatus for marking identification symbols on a wafer including: a marking means for marking identification symbols on the wafer; a reading means for reading the marked identification symbols; a comparing means for comparing data of the identification symbols which are read by the reading means with basic data on which the identification symbols are marked on the wafer, and a judging means for inspecting and judging from a result of the comparison whether the desired identification symbols are marked on the wafer or not.

Abstract translation: 一种用于在晶片上标记识别符号的装置，包括：用于在晶片上标记识别符号的标记装置; 用于读取标记的识别符号的读取装置; 用于将由读取装置读取的识别符号的数据与在晶片上标识识别符号的基本数据进行比较的比较装置，以及用于根据比较结果检查和判断所需标识符号 被标记在晶圆上。

公开(公告)号：US4162176A

公开(公告)日：1979-07-24

申请号：US715767

申请日：1976-08-19

Applicant: Akihito Tsuda

Inventor： Akihito Tsuda

IPC: H01L21/8247 ,  H01L21/28 ,  H01L29/49 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265 ,  B01J17/00 ,  H01L21/324

CPC classification number: H01L29/7886 ,  H01L21/28273 ,  H01L29/4916

Abstract: A semiconductor device for use as a non-volatile semiconductor memory is provided with a floating gate formed by ion implantation.

Abstract translation: 用作非易失性半导体存储器的半导体器件设置有通过离子注入形成的浮置栅极。

公开(公告)号：US4153883A

公开(公告)日：1979-05-08

申请号：US861331

申请日：1977-12-16

Applicant: David L. Taylor ,  Stephen A. Harris

Inventor： David L. Taylor ,  Stephen A. Harris

IPC: G11C7/10 ,  G11C11/34 ,  H03F3/213 ,  H03F3/30 ,  H03K5/02 ,  H03F3/26 ,  B01J17/00

CPC classification number: H03K5/02 ,  G11C7/1051 ,  G11C7/1057 ,  H03F3/213 ,  H03F3/3096

Abstract: An amplifier for use as on the output buffer for semiconductor memories including a fusible element added to a push-pull configuration to allow permanent conversion to an open collector configuration by blowing the fusible element or including a semiconductor element added to a push-pull configuration to cause it to have an open collector configuration and being permanently converted to a push-pull configuration by shorting the semiconductor element.

Abstract translation: 一种用于半导体存储器的输出缓冲器的放大器，包括添加到推挽配置中的可熔元件，以通过吹入可熔元件或将加入到推挽配置中的半导体元件包括在内而将其永久转换为开放式集电器配置 使其具有开放集电器配置并且通过短路半导体元件而永久地转换成推挽配置。

公开(公告)号：US4151638A

公开(公告)日：1979-05-01

申请号：US828588

申请日：1977-08-29

Applicant: John R. Welling

Inventor： John R. Welling

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  B01J17/00

CPC classification number: H01L23/49572 ,  H01L21/56 ,  H01L23/3107 ,  H01L23/3157 ,  H01L2924/0002 ,  H01L2924/01075 ,  H01L2924/09701 ,  Y10T29/49121

Abstract: a semiconductor die having bump type contact areas thereon with film strip leads bonded thereto and fired glass encapsulating only the active side of the die and the bump contact areas. The method of encapsulation includes bonding the film strip leads to the bumps of the die, coating the bumps and active area with unfired glass and firing the glass at a temperature generally below 450.degree. C. The method also includes bonding the film strip leads to the bumps and firing the glass simultaneously or firing the glass and remelting glass covering the bumps to bond the leads to the bumps through the fired glass.

Abstract translation: 具有凸起型接触区域的半导体管芯，其上粘合有膜条引线，并且仅封装了管芯的活性侧的烧结玻璃和凸点接触区域。 封装的方法包括将薄膜条导线接合到裸片的凸块上，用未烧成的玻璃涂覆凸块和有源区域，并在通常低于450℃的温度下烧制玻璃。该方法还包括将薄膜条导线 同时烧结玻璃，或者烧制玻璃并重熔玻璃覆盖凸块，以将引线通过烧制玻璃将凸块粘结在凸块上。

公开(公告)号：US4149308A

公开(公告)日：1979-04-17

申请号：US861147

申请日：1977-12-16

Applicant: Bernard Smith

Inventor： Bernard Smith

IPC: H01J9/02 ,  B01J17/00

CPC classification number: H01J9/022

Abstract: An efficient electron emitter cold cathode is formed by first placing an ype monocrystalline substrate of about 100 to about 500 microns in thickness in a furnace. The furnace is heated to about 850.degree. C. to about 900.degree. C. and an N-type layer of about 10 to 15 microns of SnO.sub.2 is deposited onto the top surface of the substrate using a suitable carrier gas. Then, a P-type layer of about 10 microns of SnO.sub.2 is deposited on the N-type layer. The furnace is then cooled at a rate of about 10.degree. C. per minute to about 600.degree. C. to form the emitter. The furnace is then cooled to room temperature and the emitter removed from the furnace. The emitter is subjected to etching and polishing to obtain a P-type layer of about 2 to 4 microns, and a nonreactive metal contact is then deposited on the P-type layer. The emitter is then completed by bonding a metal contact to the base of the N-type monocrystalline substrate.

Abstract translation: 通过首先在炉中放置约100至约500微米的N型单晶衬底形成有效的电子发射器冷阴极。 将炉子加热至约850℃至约900℃，并使用合适的载气将约10至15微米的SnO 2的N型层沉积在基板的顶表面上。 然后，在N型层上沉积约10微米SnO 2的P型层。 然后将炉子以约10℃/分钟的速率冷却至约600℃以形成发射体。 然后将炉冷却至室温，并从炉中除去发射体。 对发射体进行蚀刻和抛光以获得约2至4微米的P型层，然后在P型层上沉积非反应性金属接触。 然后通过将金属接触接合到N型单晶衬底的基底来完成发射极。

公开(公告)号：US4144636A

公开(公告)日：1979-03-20

申请号：US822589

申请日：1977-08-08

Applicant: Paul J. Burkhardt ,  Michael R. Poponiak

Inventor： Paul J. Burkhardt ,  Michael R. Poponiak

IPC: G01N27/00 ,  G01N27/12 ,  G01N27/414 ,  H01L29/66 ,  B01J17/00

CPC classification number: H01L29/66 ,  G01N27/121 ,  H01L2924/0002 ,  Y10S438/96

Abstract: A method and resulting structure for a relative humidity monitor which can be built into an integrated circuit chip. A small area on a silicon chip is made porous by anodic etching. This region is then oxidized and a metal counter electrode is deposited over part of the porous area. The surface area in the dielectric under the counter electrode is very high and because of the openness of the structure, ambient moisture can quickly diffuse into the dielectric under the electrode and adsorb onto the silicon dioxide surface. Changes in ambient humidity will then be reflected by measurable changes in capacitance or conductance of the device.

Abstract translation: 一种可以内置在集成电路芯片中的相对湿度监测器的方法和结果。 通过阳极蚀刻使硅芯片上的小区域多孔化。 然后该区域被氧化并且金属对电极沉积在多孔区域的一部分上。 相对电极下面的电介质表面积非常高，由于结构的开放性，环境湿度可以快速扩散到电极下面的电介质中并吸附到二氧化硅表面上。 环境湿度的变化将通过可测量的电容或电导率的变化来反映。

公开(公告)号：US4136436A

公开(公告)日：1979-01-30

申请号：US747031

申请日：1976-12-02

Applicant: Jack S. Kilby ,  Jay W. Lathrop ,  Wilbur A. Porter

Inventor： Jack S. Kilby ,  Jay W. Lathrop ,  Wilbur A. Porter

IPC: F24J2/04 ,  C25B1/00 ,  H01G9/20 ,  H01L31/00 ,  H01L31/042 ,  H01M8/18 ,  H01M14/00 ,  B01J17/00

CPC classification number: C25B1/003 ,  H01G9/20 ,  H01L24/24 ,  H01L31/042 ,  H01L31/062 ,  H01M14/005 ,  H01M8/186 ,  H01L2924/12032 ,  Y02E10/52 ,  Y02E60/528 ,  Y02P20/134 ,  Y02P70/56 ,  Y10S204/03

Abstract: A process for the manufacture of a light energy converter involves forming of a plurality of photovoltaic sources wherein first bodies of a first conductivity type semiconductor material each has a surface layer of a second conductivity type material and second bodies of said second conductivity type semiconductor material each has a surface layer of said first conductivity type material. The first and second bodies are intermingled in a one level layer in an insulating support. A conductive layer is applied to interconnect the first conductivity type material of all said first bodies with the second conductivity type material of all said second bodies. An electrolyte may wet such sources where, upon exposure to light, the sources cause a current to flow in the electrolyte producing an electrochemical reaction. The products of this reaction where the electrolyte is a solution such as aqueous hydrogen iodide, and the hydrogen produced by the electrochemical reaction may be stored, burned as a fuel or used in a fuel cell to produce electrical energy.

Abstract translation: 一种用于制造光能转换器的方法包括形成多个光伏源，其中第一导电类型半导体材料的第一主体各自具有第二导电类型材料的表面层和所述第二导电类型半导体材料的第二主体 具有所述第一导电类型材料的表面层。 第一和第二物体混合在绝缘支撑体中的一层中。 施加导电层以将所有所述第一主体的第一导电类型材料与所有所述第二主体的第二导电类型材料互连。 电解质可以润湿这样的源，其中当暴露于光时，源引起电流在电解质中流动，产生电化学反应。 电解质是诸如碘化氢水溶液和通过电化学反应产生的氢的反应的产物可以作为燃料储存，燃烧或用于燃料电池中以产生电能。

公开(公告)号：US4135290A

公开(公告)日：1979-01-23

申请号：US863770

申请日：1977-12-23

Applicant: John C. Evans, Jr.

Inventor： John C. Evans, Jr.

IPC: H01L31/0224 ,  H01L31/07 ,  H01L31/072 ,  H01L31/18 ,  B01J17/00

CPC classification number: H01L31/074 ,  H01L31/022425 ,  H01L31/07 ,  H01L31/072 ,  H01L31/18 ,  H01L31/1804 ,  H01L31/184 ,  Y02E10/544 ,  Y02E10/547 ,  Y02P70/521 ,  Y10S148/153

Abstract: A heterojunction or Schottky barrier photovoltaic device comprising a conductive base metal layer compatible with and coating predominately the exposed surface of the p-type substrate of the device such that a back surface field region is formed at the interface between the device and the base metal layer, a transparent, conductive mixed metal oxide layer in integral contact with the n-type layer of the heterojunction or Schottky barrier device having a metal alloy grid network of the same metal elements of the oxide constituents of the mixed metal oxide layer embedded in the mixed metal oxide layer, an insulating layer which prevents electrical contact between the conductive metal base layer and the transparent, conductive metal oxide layer, and a metal contact means covering the insulating layer and in intimate contact with the metal grid network embedded in the transparent, conductive oxide layer for conducting electrons generated by the photovoltaic process from the device.

Abstract translation: 一种异质结或肖特基势垒光伏器件，包括与器件的p型衬底的暴露表面相容并主要涂覆的导电基底金属层，使得在器件和基底金属层之间的界面处形成背面场区域 ，与异质结或肖特基势垒器件的n型层整体接触的透明导电混合金属氧化物层，其具有嵌入混合的混合金属氧化物层的氧化物组分的相同金属元素的金属合金网格 金属氧化物层，绝缘层，其防止导电金属基底层和透明导电金属氧化物层之间的电接触，以及覆盖绝缘层的金属接触装置，并且与嵌入透明导电的金属网格网络紧密接触 氧化层，用于从该器件导入由光伏处理产生的电子。

公开(公告)号：US4127931A

公开(公告)日：1978-12-05

申请号：US848015

申请日：1977-11-02

Applicant: Hiroshi Shiba

Inventor： Hiroshi Shiba

IPC: H01L21/225 ,  H01L21/285 ,  H01L21/321 ,  H01L21/331 ,  H01L21/336 ,  H01L23/532 ,  B01J17/00

CPC classification number: H01L29/66606 ,  H01L21/2257 ,  H01L21/28525 ,  H01L21/32105 ,  H01L23/53271 ,  H01L29/66272 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/117 ,  Y10S148/124

Abstract: In a method for fabricating a semiconductor device, a polycrystalline film deposited on a main surface of a substrate is subjected to selective oxidation to form polycrystalline silicon electrode wiring paths separated by silicon oxide. An impurity of a conductivity type opposite to that of the substrate is introduced through at least one of the wiring paths into the substrate. Also disclosed is a novel semiconductor device fabricated according to this process which has a reduced junction area and a shortened junction-to-electrode distance.

Abstract translation: 在制造半导体器件的方法中，沉积在衬底的主表面上的多晶膜经受选择性氧化以形成由氧化硅分离的多晶硅电极布线路径。 通过至少一个布线路径将与衬底相反的导电类型的杂质引入到衬底中。 还公开了根据该方法制造的新颖的半导体器件，其具有减小的结面积和缩短的结至电极距离。