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公开(公告)号：US20200159616A1
公开(公告)日：2020-05-21
申请号：US16752859
申请日：2020-01-27
IPC分类号： G06F11/10 , G11C29/00 , G06F11/08 , G06F11/07 , G11C29/56 , G11C29/52 , H03M13/00 , H03M13/37 , G11C11/56 , H03M13/11
摘要： The present disclosure includes apparatuses and methods for estimating an error rate associated with memory. A number of embodiments include sensing data stored in a memory, performing an error detection operation on the sensed data, determining a quantity of parity violations associated with the error detection operation, and estimating an error rate associated with the memory based on the determined quantity of parity violations.
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公开(公告)号：US10650908B2
公开(公告)日：2020-05-12
申请号：US15955026
申请日：2018-04-17
申请人： SK hynix Inc.
发明人： Young Mok Jung
IPC分类号： H03M13/00 , G11C29/44 , G11C11/409 , G11C29/20 , G11C29/36 , H01L21/66 , G11C29/00 , G11C29/02 , G11C29/40 , G11C29/12 , G11C29/04 , G11C29/56
摘要： A semiconductor device and a system including the semiconductor device are disclosed, which relate to a technology for detecting a defective or failed part during a probe test of the semiconductor device. The semiconductor device includes a test controller configured to perform counting of a read flag signal during activation of a test signal and to control a data mask signal to be toggled at an N-th activation time of the read flag signal. The semiconductor device further includes a cell array configured to receive and store an output signal of the test controller through a data line during a write operation and to output the stored data to a test device during a read operation.
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公开(公告)号：US10650891B2
公开(公告)日：2020-05-12
申请号：US16419895
申请日：2019-05-22
发明人： Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
摘要： Methods, systems, and devices for non-contact electron beam probing techniques, including at one or more intermediate stages of fabrication, are described. One subset of first access lines may be grounded and coupled with one or more memory cells. A second subset of first access lines may be floating and coupled with one or more memory cells. A second access line may correspond to each first access line and may be configured to be coupled with the corresponding first access line, by way of one or more corresponding memory cells, when scanned with an electron beam. A leakage path may be determined by comparing an optical pattern generated in part by determining a brightness of each scanned access line and comparing the generated optical pattern with a second optical pattern.
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44.发明授权公开(公告)号：US10607670B2
公开(公告)日：2020-03-31
申请号：US15794177
申请日：2017-10-26
申请人： Rambus Inc.
发明人： Thomas Giovannini , Scott Best , Lei Luo , Ian Shaeffer
摘要： A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.
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45.发明申请公开(公告)号：US20200075119A1
公开(公告)日：2020-03-05
申请号：US16675783
申请日：2019-11-06
发明人： Aravindan J. BUSI , John R. GOSS , Paul J. GRZYMKOWSKI , Krishnendu MONDAL , Kiran K. NARAYAN , Michael R. OUELLETTE , Michael A. ZIEGERHOFER
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
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公开(公告)号：US10553302B2
公开(公告)日：2020-02-04
申请号：US15798858
申请日：2017-10-31
发明人： Aravindan J. Busi , John R. Goss , Paul J. Grzymkowski , Krishnendu Mondal , Kiran K. Narayan , Michael R. Ouellette , Michael A. Ziegerhofer
摘要： A BIST engine configured to store a per pattern based fail status during memory BIST run and related processes thereof are provided. The method includes testing a plurality of patterns in at least one memory device and determining which of the plurality of patterns has detected a fail during execution of each pattern. The method further includes storing a per pattern based fail status of each of the detected failed patterns.
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公开(公告)号：US10529437B2
公开(公告)日：2020-01-07
申请号：US16039112
申请日：2018-07-18
申请人： SK hynix Inc.
发明人： Soo Young Jang , Jin Youp Cha
摘要： A system may include a first semiconductor apparatus and a second semiconductor apparatus. Each of the first and second semiconductor apparatuses may receive reference data and a first clock signal. The first semiconductor apparatus may generate a first internal clock signal from the first clock signal, and may output the reference data as transmission data based on the first internal clock signal. The second semiconductor apparatus may generate a second internal clock signal from the first clock signal, and may receive the transmission data based on the second internal clock signal. The second semiconductor apparatus may generate an error detection signal based on the received data and the reference data.
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公开(公告)号：US20190378590A1
公开(公告)日：2019-12-12
申请号：US16244890
申请日：2019-01-10
发明人： SUNG-HO JOO , Gyu-Yeol Kim , Jae-Young Lee , Chang-Hyun Cho
IPC分类号： G11C29/56 , G11C29/10 , G01R31/3183 , G01R31/317
摘要： A test interface board includes one or more relay circuits and a synchronization signal generator. The relay circuits duplicate a test signal from an automated test equipment (ATE), apply duplicated test signals to each of a plurality of devices under test (DUTs) through one of corresponding channels, and provide the ATE with a plurality of test result signals received from each of the DUTs in response to the duplicated test signals. The synchronization signal generator receives a plurality of status signals from each of the DUTs and provides a timing synchronization signal to the ATE. Each of the status signals indicates a completion of a test operation in one of the DUTs, the test operation is associated with the test signal, and the synchronization signal generator activates the timing synchronization signal when all of the status signals indicate the completion of the test operation.
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公开(公告)号：US20190362804A1
公开(公告)日：2019-11-28
申请号：US16213771
申请日：2018-12-07
申请人： SK hynix Inc.
发明人： Yong Seop KIM
IPC分类号： G11C29/56 , G01R31/3181 , G01R31/3185
摘要： A semiconductor device may include a plurality of chips and a test pad. The plurality of chips may check parity bits of a plurality of pattern signals activated in units of specific bits and store test result signals generated by the checking of the parity bits. The plurality of chips may output an error detection signal when an error is detected from any of the test result signals. The test pad may output the error detection signal received from the plurality of chips to an external part. The plurality of chips may be commonly coupled to at least one connection line such that, when the error detection signal is output from at least one of the plurality of chips, the outputted error detection signal s output through the test pad.
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公开(公告)号：US20190341122A1
公开(公告)日：2019-11-07
申请号：US16419885
申请日：2019-05-22
发明人： Amitava Majumdar , Rajesh Kamana , Hongmei Wang , Shawn D. Lyonsmith , Ervin T. Hill , Zengtao T. Liu , Marlon W. Hug
摘要： Methods, systems, and devices for non-contact measurement of memory cell threshold voltage, including at one or more intermediate stages of fabrication, are described. One access line may be grounded and coupled with one or more memory cells. Each of the one or more memory cells may be coupled with a corresponding floating access line. A floating access line may be scanned with an electron beam configured to set the floating access line to a particular surface voltage at the scanned bit line, and the threshold voltage of the corresponding memory cell may be determined based on whether setting the scanned bit line to the surface voltage causes a detectable amount current to flow through the corresponding memory cell.
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