-
公开(公告)号：US11249532B2
公开(公告)日：2022-02-15
申请号：US17155061
申请日：2021-01-21
发明人： Eun Ryeol Baek , Yoon Young Lee
IPC分类号： G06F1/32 , G06F1/08 , G06F1/10 , G06F1/12 , G06F1/3206
摘要： A display device includes: a display panel including scan lines, a first power line, a second power line, and pixels connected to the scan lines and the first and second power lines; a gate driver to sequentially provide scan signals to the scan lines based on a clock signal; and a power supply including transistors to convert an input power voltage into a first power voltage through a switching operation of the transistors and to supply the first power voltage to the first power line through a first output terminal. In response to an amount of current flowing through the pixels being less than a first reference current amount, the power supply is configured to change one or more of an off-duty of at least one of the transistors, a channel capacitance of at least one of the transistors, a switching frequency of at least one of the transistors, and a slew rate of at least one of control signals for the transistors.
-
公开(公告)号：US11234307B2
公开(公告)日：2022-01-25
申请号：US16907054
申请日：2020-06-19
发明人： Ziv Magoz
摘要： A powering circuit for a diode light source includes an inductor charged through an on/off switch. The charging occurs during a charging cycle for a controllable amount of time when the on/off switch is closed. The energy of the charged inductor is used to power the semiconductor light source by opening the on/off switch. In such a driving configuration, the ringing is nearly constant and thus may be suppressed using an appropriately configured circuit.
-
公开(公告)号：US11226925B2
公开(公告)日：2022-01-18
申请号：US16674138
申请日：2019-11-05
申请人： Altera Corporation
发明人： Chee Hak Teh , Arifur Rahman
摘要： A multichip package having a main die coupled to one or more daughter dies is provided. The main die may include embedded universal interface blocks (UIB) each of which can be used to interface with a corresponding daughter die to support high bandwidth parallel or serial communications. Each UIB may include an integrated processor subsystem and associated pattern sequencing logic to perform interface initialization and margining operations. Each UIB may perform simultaneous accesses to a daughter die across one or more channels. Each UIB may also include multiple phase-locked loop circuits for providing different clock signals to different portions of the UIB and a 2× clock phase generation logic. Each UIB may include multiple IO modules, each of which may optionally include its own duty cycle correction circuit. Each IO module may include buffer circuits, each of which may have a de-emphasis control logic for adjusting buffer drive strength.
-
公开(公告)号：US20220014098A1
公开(公告)日：2022-01-13
申请号：US16984577
申请日：2020-08-04
发明人： Fu-Yan Xie , Bing-Chen Wu , Tsung-Te Liu
摘要： A switched-capacitor DC-DC voltage converter and a control method thereof. The switched-capacitor DC-DC voltage converter comprises at least one switch array, comprising a capacitor and at least one switch group, wherein the switch group comprises a plurality of power switches connected to one another in parallel, and one end of the capacitor is electrically connected to the switch group; and a control circuit, converting an input control signal into a control signal set, and outputting the control signal set to the switch group, and the control signal set comprises a plurality of control signals with phase delayed sequentially and the duty cycle reduced sequentially.
-
公开(公告)号：US11218154B2
公开(公告)日：2022-01-04
申请号：US16964369
申请日：2019-01-31
发明人： Seungjoon Yoon , Cheolho Lee
摘要： An integrated circuit according to an embodiment of the disclosure may include a plurality of function blocks, a spread spectrum clock (SSC) generator that generates a spread spectrum clock based on a frequency modulation rate value, a clock distribution circuit that distributes the generated spread spectrum clock into the plurality of function blocks, a memory that stores predetermined frequency modulation rate values respectively corresponding to the plurality of function blocks, and a control circuit, and the control circuit may be configured to generate the spread spectrum clock based on a smaller frequency modulation rate value among a first frequency modulation rate value and a second frequency modulation rate value respectively corresponding to a first function block and a second function block, which are operating, from among the plurality of function blocks. Moreover, various embodiment found through the present disclosure are possible.
-
公开(公告)号：US11210443B2
公开(公告)日：2021-12-28
申请号：US15841064
申请日：2017-12-13
申请人： Intel Corporation
发明人： Herman Henry Schmit
IPC分类号： G06F30/3312 , G06F1/10 , H03K19/003 , H03K19/096 , H03K19/177 , G06F30/35 , G06F30/327 , G06F30/396 , G06F119/12
摘要： The present disclosure provides systems and methods for improving operation of integrated circuit device including a logic region, which includes a plurality of logic gates that operate based at least in part on a clock signal to facilitate providing a target function, and a clock tree, which includes a clock switch block that receives a source clock signal from a clock source and a branch communicatively coupled between the clock switch block and the logic region, in which the branch operates to provide the clock signal to the logic region based at least in part on the source clock signal and one or more tunable delay buffers, disposed at junctures of the clock network, that operate to apply a delay to the clock signal based at least in part on a clock skew expected to be introduced by the branch.
-
公开(公告)号：US11199621B2
公开(公告)日：2021-12-14
申请号：US16278006
申请日：2019-02-15
申请人： NXP B.V.
摘要： In accordance with a first aspect of the present disclosure, a transponder is provided, comprising: a frequency detector configured to monitor an output frequency of a clock-stop sensor of said transponder, wherein said frequency detector is further configured to determine if said output frequency falls within a response detection frequency range of an external reader, and a frequency shifter configured to shift, in response to the frequency detector determining that the output frequency falls within said response detection frequency range, said output frequency to a value outside said response detection frequency range. In accordance with a second aspect of the present disclosure, a corresponding method of operating a transponder is conceived. In accordance with a third aspect of the present disclosure, a corresponding computer program is provided.
-
公开(公告)号：US20210357353A1
公开(公告)日：2021-11-18
申请号：US17347282
申请日：2021-06-14
发明人： Akihiro Suzuki , Masami Nakashima , Masuo Inui , Koji Okada , Takeo Zaitsu , Takashi Shimizu , Shinichi Yamamoto , Kazuhiro Tomita , Susumu Kuroda
IPC分类号： G06F13/42 , H03K5/156 , G06F13/364 , G06F1/3287 , G06F1/04 , G06F1/08 , G06F1/3237 , G06F1/10 , G06F1/12 , G06F13/40
摘要： An on-vehicle system comprises a Clock Extension Peripheral Interface (CXPI) bus and a device coupled to the CXPI bus as a slave node. The device comprises a transceiver configured to: generate a first signal by delaying an inverted signal of a transmission data signal: generate a second signal based on the transmission data signal, where the second signal has a low slew rate: selectively output the first signal or the second signal as a third signal, in response to a selector signal: and generate a clock signal in response to the third signal, where the clock signal is at a high level when the third signal is at a low level, and where the clock signal is at the low level when the third signal is at the high level.
-
49.发明授权公开(公告)号：US11175928B2
公开(公告)日：2021-11-16
申请号：US17042896
申请日：2018-12-11
发明人： Jun Deng
摘要： The present invention relates to the technical field of electronic communication, and specifically disclosed thereby are a master-slave configuration communication protocol, a method for improving compatibility and an electronic device. The master-slave configuration communication protocol comprises: electrically connecting one GPIO pin of a master configuration to at least one kind of slave configuration; the master configuration sending a mock address to the slave configuration through the GPIO pin; and the slave configuration receiving the mock address and comparing the mock address with its native address, if the mock address matches the native address, the slave configuration sends its parameter information to the master configuration. The master-slave configuration communication protocol provided by embodiments of the present invention may enable the master configuration to obtain parameter information of one or more kinds of slave configurations connected to the master configuration through one GPIO pin, so that the master configuration is allowed to be compatible with multiple slave configurations, and thus the GPIO pin resources are greatly saved. The present invention also provides a method for improving compatibility and an electronic device.
-
公开(公告)号：US20210344344A1
公开(公告)日：2021-11-04
申请号：US16862071
申请日：2020-04-29
申请人： Apple Inc.
IPC分类号： H03K19/094 , G06F1/10 , H03K17/284
摘要： Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.
-
-
-
-
-
-
-
-
-
搜索结果
2830 条记录 (耗时 0.035 秒)