公开(公告)号：US10025534B1

公开(公告)日：2018-07-17

申请号：US15848374

申请日：2017-12-20

Applicant: Seagate Technology LLC

Inventor： Yan Naing ,  Harry Tiotantra ,  PohGuat Bay ,  Thein Than Zaw ,  CheeHou Peng

IPC: G11B5/09 ,  G06F3/06 ,  G06F12/0868 ,  G11B20/10 ,  G11B20/12

Abstract: Implementations disclosed herein include a method comprising receiving a TRIM request for a media cache in a storage media from a host, determining whether a TRIM range in the TRIM request overlaps with an active operation, invalidating the TRIM range responsive to determining that the TRIM range does not overlap with an active operation, and inserting at least one null node in the media cache. The method may comprise receiving a host read request, performing a media cache search for a read LBA range, and determining where data is located. If all the data is located in the media cache, the system reads from the media cache. If the data is located in a null node, patterning for the null node occurs. If the data is located partially in the main store, the media cache, or a null node, the data may be read, combined, and returned to the host.

公开(公告)号：US10020012B1

公开(公告)日：2018-07-10

申请号：US15798541

申请日：2017-10-31

Applicant: Seagate Technology LLC

Inventor： Aaron P. Weyer ,  Bruce Douglas Buch ,  Kyaw Sin Maung ,  Jon D. Trantham ,  Nicholas Paul Mati

IPC: G11B5/09 ,  G11B5/55 ,  G11B5/596 ,  G06F13/42

CPC classification number: G11B5/5526 ,  G06F13/42 ,  G11B5/59616

Abstract: First and second servo control processors are coupled to respective first and second actuators that independently position first and second heads over one or more disks of a data storage drive. The first and second servo control processors are further coupled to first and second low-latency ports. First and second unidirectional buses couple the first and second low-latency ports. The first and second unidirectional busses are operable to isochronously exchange servo positioning data between the first and second servo control processors. The first and second servo control processors each use the servo positioning data to compensate for movement caused by another of the first and second servo control processors.

公开(公告)号：US20180182433A1

公开(公告)日：2018-06-28

申请号：US15887338

申请日：2018-02-02

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： JUNGHWAN SHIN ,  JAE IK SONG ,  DONG HYUCK SHIN ,  EUN YEONG HONG

IPC: G11B20/18

CPC classification number: G11B20/1816 ,  G11B2020/1823 ,  G11B2020/1826 ,  G11B2020/183

Abstract: Systems and methods for forward corrupted track detection and by-pass are described. In one embodiment, a storage system comprising a storage controller performs a read operation for a target track of a shingled magnetic recording (SMR) disk drive and detects a read operation failure of the read operation for the target track. The storage controller also performs a boundary track read operation on one or more tracks including or adjacent to the target track and detect a forward corruption area based on the boundary track read operation. In another embodiment, a method is provided that includes detecting a read operation failure of a read operation for a track of a disk drive and performing a boundary track read operation on one or more tracks including or adjacent to the target track. The method also includes detecting a forward corruption area based on the boundary track read operation.

公开(公告)号：US20180182432A1

公开(公告)日：2018-06-28

申请号：US15388042

申请日：2016-12-22

Applicant: Seagate Technology LLC

Inventor： Xiong Liu ,  Quan Li ,  Kai Yang

IPC: G11B20/12 ,  G11B20/18 ,  G11B5/596

CPC classification number: G11B20/1217 ,  G11B5/596 ,  G11B5/59633 ,  G11B5/59638 ,  G11B5/59644 ,  G11B5/59688 ,  G11B20/1816 ,  G11B2020/1218 ,  G11B2020/1238

Abstract: A data storage device can employ shingled magnetic recording with data tracks oriented in order to optimize operational parameters, such as bit error rate. A data storage device can consist of a plurality of data tracks overlapping in a band on a data storage medium. First, second, and third data tracks of the band can be respectively separated by a uniform first track pitch during testing the band for an operational parameter. The first track pitch may then be adjusted to provide at least two different adjusted track pitches with each track pitch measured between longitudinal centerlines of adjacent data tracks of the band.

公开(公告)号：US10002046B2

公开(公告)日：2018-06-19

申请号：US15238839

申请日：2016-08-17

Applicant: Seagate Technology LLC

Inventor： Earl T. Cohen

IPC: G06F11/10 ,  H03M13/11 ,  G06F3/06 ,  G11C29/52 ,  H03M13/09 ,  H03M13/15 ,  H03M13/19

CPC classification number: G06F11/1068 ,  G06F3/061 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0658 ,  G06F3/0676 ,  G06F3/0679 ,  G06F11/1012 ,  G06F11/1048 ,  G06F11/1072 ,  G06F2206/1014 ,  G11C29/52 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1515 ,  H03M13/152 ,  H03M13/19

Abstract: An SSD controller maintains a zero count and a one count, and/or in some embodiments a zero/one disparity count, for each read unit read from an SLC NVM (or the lower pages of an MLC). In an event that the read unit is uncorrectable in part due to a shift in the threshold voltage distributions away from their nominal distributions, the maintained counts enable a determination of a direction and/or a magnitude to adjust a read threshold to track the threshold voltage shift and restore the read data zero/one balance. In various embodiments, the adjusted read threshold is determined in a variety of described ways (counts, percentages) that are based on a number of described factors (determined threshold voltage distributions, known stored values, past NVM operating events). Extensions of the forgoing techniques are described for MLC memories.

公开(公告)号：US09998136B1

公开(公告)日：2018-06-12

申请号：US15436709

申请日：2017-02-17

Applicant: Seagate Technology LLC

Inventor： Zheng Wu ,  Jason Vincent Bellorado ,  Marcus Marrow

IPC: H03M1/18 ,  H03M1/12 ,  G11B20/10

CPC classification number: H03M1/18 ,  G11B20/10027 ,  G11B20/10037 ,  G11B20/10222 ,  H03M1/12 ,  H03M1/124

Abstract: An apparatus may include a circuit configured to generate, by an analog to digital converter (ADC), one or more ADC samples based on an input signal. The circuit may be further configured to generate a first estimated signal using a first channel pulse response estimation with a gain constraint based on the one or more ADC samples and generate a second estimated signal using a second channel pulse response estimation with a phase constraint based on the one or more ADC samples.

公开(公告)号：US09997192B1

公开(公告)日：2018-06-12

申请号：US15599265

申请日：2017-05-18

Applicant: Seagate Technology LLC

Inventor： Chris R. Fulkerson ,  Abhay T. Kataria

IPC: G11B19/04 ,  G11B20/18 ,  G11B20/10

CPC classification number: G11B19/041 ,  G11B20/10009 ,  G11B20/1217 ,  G11B20/18 ,  G11B2020/10898 ,  G11B2020/1869

Abstract: Embodiments described herein provide an apparatus that is operable with a disk drive. The apparatus includes a memory device operable to store a plurality of bit sets. Each bit set identifies a track and a sector of the disk drive and a number of times that the track of the disk drive has been written. A controller of the disk drive is operable to increment the number when the track is written. Each bit set comprises a number of bits that is established according to track location of the disk drive.

公开(公告)号：US09996416B2

公开(公告)日：2018-06-12

申请号：US15269605

申请日：2016-09-19

Applicant: SEAGATE TECHNOLOGY LLC

Inventor： Haitao Xia ,  Fan Zhang ,  Shu Li ,  Jun Xiao

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/00 ,  G11C29/52 ,  G06F3/06

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1008 ,  G06F11/1012 ,  G11C29/52 ,  H03M13/1111 ,  H03M13/1128 ,  H03M13/1142 ,  H03M13/3723 ,  H03M13/3746 ,  H03M13/6337

Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for accessing a data set from a solid state storage device, using a data decoding circuit to apply a data decoding algorithm to the data set to yield a decoded output, where the decoded output includes at least one error, identifying at least one critical location in the data set, and estimating a voltage associated with the data in the data set corresponding to the critical location.

公开(公告)号：US09990951B2

公开(公告)日：2018-06-05

申请号：US15150378

申请日：2016-05-09

Applicant: Seagate Technology LLC

Inventor： Bin Lu

IPC: G11B5/66 ,  G11B5/667

CPC classification number: G11B5/66 ,  G11B5/667 ,  G11B5/855

Abstract: Provided herein is an apparatus including a top continuous layer and a bottom continuous layer under the top continuous layer. The top continuous layer and the bottom continuous layer are antiferromagnetically coupled. A number of granular columns are under the bottom continuous layer. The number of granular columns include at least a first granular layer under the bottom continuous layer and a second granular layer also under the first granular layer. The first granular layer and the second granular layer are separated by a non-magnetic spacer. The first granular layer and the second granular layer are ferromagnetically coupled. The first granular layer is antiferromagnetically coupled to the bottom continuous layer.

公开(公告)号：US09990941B1

公开(公告)日：2018-06-05

申请号：US15350797

申请日：2016-11-14

Applicant: Seagate Technology LLC

Inventor： Victor Sapozhnikov ,  Mohammed Shariat Ullah Patwari ,  Jason B Gadbois ,  Taras Grigorievich Pokhil

IPC: G11B5/187 ,  G11B5/265 ,  G11B5/02

CPC classification number: G11B5/265 ,  G11B5/02 ,  G11B5/2651

Abstract: A method of forming a read head. The method includes forming first and second read sensors. A first read measurement is performed on a storage medium using the first read sensor. A second read measurement is performed on the storage medium using the second read sensor. Based on a comparison of the first and second read measurements to a predetermined quantity, either the first read sensor or the second read sensor is selected to be operational in a data storage device.