公开(公告)号：US20240314973A1

公开(公告)日：2024-09-19

申请号：US18671881

申请日：2024-05-22

Applicant: Intel Corporation

Inventor： Chen ZHANG ,  Xiang QUE ,  Yang YAO ,  Yuehong FAN ,  Guangying ZHANG ,  Liguang DU ,  Shaorong ZHOU ,  Chuanlou WANG ,  Yingqiong BU ,  Yue YANG

IPC: H05K7/20 ,  H05K1/02

CPC classification number: H05K7/20236 ,  H05K1/0203 ,  H05K7/20272 ,  H05K7/20281 ,  H05K7/20409 ,  H05K7/20763 ,  H05K7/20263

Abstract: An apparatus is described that includes an immersion bath chamber and a cover that is to seal the immersion bath chamber. An apparatus is described that includes an immersion bath chamber and an installable/removable transfer member. The installable/removable transfer member has fluidic connectors designed to couple to respective warmed fluid flow output ports of pluggable units to be cooled in the immersion bath chamber and having respective backplane interface designs. An apparatus is described that includes an immersion bath chamber and an overflow chamber. The overflow chamber is to receive an overflow of liquid coolant from the immersion bath chamber, wherein a first exit flow channel from the overflow chamber is coupled to a second exit fluid flow channel from the immersion bath chamber through a valve, wherein, an opening of the valve is controllable to vary a gravitational fluid flow within the immersion bath chamber.

公开(公告)号：US20240314213A1

公开(公告)日：2024-09-19

申请号：US18410707

申请日：2024-01-11

Applicant: Intel Corporation

Inventor： Steffen Schulz ,  Patrick Koeberl ,  Alpa Narendra Trivedi ,  Scott Weber

IPC: H04L67/51 ,  H04L9/40 ,  H04L67/00

CPC classification number: H04L67/51 ,  H04L63/08 ,  H04L67/00

Abstract: A multitenancy system that includes a host provider, a programmable device, and multiple tenants is provided. The host provider may publish a multitenancy mode sharing and allocation policy that includes a list of terms to which the programmable device and tenants can adhere. The programmable device may include a secure device manager configured to operate in a multitenancy mode to load a tenant persona into a given partial reconfiguration (PR) sandbox region on the programmable device. The secure device manager may be used to enforce spatial isolation between different PR sandbox regions and temporal isolation between successive tenants in one PR sandbox region.

公开(公告)号：US20240312869A1

公开(公告)日：2024-09-19

申请号：US18183505

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Tongyan Zhai ,  Telesphor Kamgaing ,  Min Suet Lim

IPC: H01L23/473 ,  H01L23/00 ,  H01L23/528

CPC classification number: H01L23/473 ,  H01L23/528 ,  H01L24/32 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225

Abstract: Described herein are integrated circuit devices that include semiconductor devices near the center of the device, rather than towards the top or bottom of the device. In this arrangement, heat can become trapped inside the device. A microfluidic cooling layer is formed near a top or front the device, e.g., over the semiconductor devices and any front side interconnect structures, to transfer heat away from the semiconductor devices.

公开(公告)号：US20240312853A1

公开(公告)日：2024-09-19

申请号：US18121331

申请日：2023-03-14

Applicant: Intel Corporation

Inventor： Sashi S. KANDANUR ,  Srinivas V. PIETAMBARAM ,  Darko GRUJICIC ,  Brandon C. MARIN ,  Suddhasattwa NAD ,  Benjamin DUONG ,  Gang DUAN ,  Mohammad Mamunur RAHMAN ,  Numair AHMED

IPC: H01L23/15 ,  H01L23/498

CPC classification number: H01L23/15 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838

Abstract: Embodiments herein relate to systems, apparatuses, techniques and/or processes for creating a substrate out of a plurality of layers of glass, where the substrate includes one or more vias that extend through each of the plurality of layers of glass. In embodiments, a high aspect ratio via may be constructed through the substrate by electrically coupling the individual vias. Other embodiments may be described and/or claimed.

公开(公告)号：US20240312819A1

公开(公告)日：2024-09-19

申请号：US18185427

申请日：2023-03-17

Applicant: Intel Corporation

Inventor： Hong Seung YEON ,  Mariano PHIELIPP ,  Yi LI ,  Minglu LIU ,  Robin McREE ,  Yosuke KANAOKA ,  Gang DUAN

IPC: H01L21/68 ,  H01L21/67

CPC classification number: H01L21/68 ,  H01L21/67259

Abstract: A method for real-time offset adjustment of a semiconductor die placement comprising: obtaining or receiving operational parameters of a die mounting tool in real-time, wherein the die mounting tool is configured for placing the semiconductor die on a panel; predicting an offset adjustment of the semiconductor die placement based on the operational parameters; and determining semiconductor die placement coordinates based on an original die placement and the offset adjustment.

公开(公告)号：US20240312130A1

公开(公告)日：2024-09-19

申请号：US18571146

申请日：2023-01-20

Applicant: Intel Corporation

Inventor： Stephen PALERMO ,  Bhupesh AGRAWAL ,  Valerie PARKER

IPC: G06T17/00 ,  H04N21/2187

CPC classification number: G06T17/00 ,  H04N21/2187

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for location-aware virtual reality (VR). An example apparatus disclosed herein is to determine a first location of a first VR device and a second location of a second VR device. The disclosed example apparatus is to identify a preset guardian boundary corresponding to a VR live stream based on at least one of first credentials associated with the first VR device or second credentials associated with the second VR device. Additionally, the disclosed example apparatus is to, after a determination that the first location and the second location satisfy the preset guardian boundary, at least one of execute or instantiate an instance of a VR live stream application associated with the VR live steam based on the first location and the second location, the first VR device and the second VR device to be associated with the VR live stream application.

公开(公告)号：US20240312107A1

公开(公告)日：2024-09-19

申请号：US18478229

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Mrutunjayya Mrutunjayya ,  SungYe Kim

IPC: G06T15/00

CPC classification number: G06T15/005 ,  G06T2210/52

Abstract: Described herein are techniques to preserve G-buffer and optical flow data in UV coordinate space. The G-buffer and optical flow data can be used to correct disocclusion artifacts in frames generated via a neural network.

公开(公告)号：US20240311951A1

公开(公告)日：2024-09-19

申请号：US18478286

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Selvakumar Panneer ,  Sarthak Rajesh Shah ,  Nilesh Jain ,  John Feit

IPC: G06T1/20 ,  G06F9/50

CPC classification number: G06T1/20 ,  G06F9/5038

Abstract: Described herein is a graphics processor configured to perform time based frame predication to bypass execution of a command buffer based on a comparison with time stamps stored in a time stamp buffer that tracks execution time for command buffers. The graphics processors can bypass a frame that will not complete in time for a target display update and trigger neural frame generation to generate the frame data for the bypassed command buffer. Dynamic render scaling is also described.

公开(公告)号：US20240311537A1

公开(公告)日：2024-09-19

申请号：US18120857

申请日：2023-03-13

Applicant: Intel Corporation

Inventor： David Kehlet ,  Nij Dorairaj ,  Shuanghong Sun

IPC: G06F30/31

CPC classification number: G06F30/31

Abstract: A computer system is provided for protecting an original circuit design for an integrated circuit. The computer system includes a logic circuit replacement tool that generates a redacted circuit design for the integrated circuit by replacing logic circuits in the original circuit design with first and second configurable circuits that perform logic functions of the logic circuits when a bitstream stored in storage circuits configures the first and the second configurable circuits. The logic circuit replacement tool couples one of the storage circuits that stores a bit in the bitstream to an input in each of the first and the second configurable circuits in the redacted circuit design.

公开(公告)号：US20240311312A1

公开(公告)日：2024-09-19

申请号：US18121972

申请日：2023-03-15

Applicant: INTEL CORPORATION

Inventor： Jason BRANDT ,  Ido OUZIEL ,  Michael CHYNOWETH ,  Raoul RIVAS TOLEDANO ,  Gilbert NEIGER ,  Andreas KLEEN ,  Jacob DOWECK ,  Andrew NELSON

IPC: G06F12/1045

CPC classification number: G06F12/1045 ,  G06F2212/682

Abstract: An apparatus and method are described for reduced power TLB management. For example, one embodiment of a processor comprises: a plurality of cores; a first core of the plurality of cores comprising: a first translation lookaside buffer (TLB) to store address translations associated with page table walk operations, and power management logic to cause the first core to enter into a first low power state in which the address translations in the first TLB are no longer valid, wherein prior to entering into the low power state, the first core is to write an indication in a memory location that the first TLB no longer contains valid address translations; a second core of the plurality of cores to perform an operation requiring invalidation of one or more of the address translations previously stored in the first TLB, the second core to determine whether to transmit a request to the first core to invalidate the one or more address translations based on the indication.