公开(公告)号：US20030234446A1

公开(公告)日：2003-12-25

申请号：US10371397

申请日：2003-02-20

Applicant: STMicroelectronics SA

Inventor： Jean-Luc Diot ,  Christophe Prior ,  Jerome Teysseyre ,  Jean-Pierre Moscicki

IPC: H01L023/48 ,  H01L023/28 ,  H01L021/44

CPC classification number: H01L21/565 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The leadframe has a perforation to form, between a central platform and a peripheral part located a certain distance apart, radiating elongate leads. The leadframe has, on its rear face that comes into contact with a bearing surface of a mold, at least one recess and a groove for connecting this recess to the perforation.

Abstract translation: 引线框架具有在中心平台和位于一定距离之间的周边部分之间形成穿孔，辐射细长的引线。 所述引线框在其与所述模具的支承表面接触的后表面上具有至少一个凹部和用于将所述凹部连接到所述穿孔的凹槽。

公开(公告)号：US20030233605A1

公开(公告)日：2003-12-18

申请号：US10424166

申请日：2003-04-25

Applicant: STMicroelectronics SA

Inventor： Charaf Hanna

IPC: G11C029/00

CPC classification number: H03M13/2785 ,  H03M13/2707 ,  H03M13/2764

Abstract: A method for interlacing digital data to reduce transmission errors includes dividing a stream of digital data into consecutive blocks of bits, and interlacing each block of bits by writing to an interlacing table. The interlacing table is arranged in the form of rows and columns of memory addresses, with a number of the rows and columns corresponding to predetermined interlacing parameters. The access sequences to the memory addresses for interlacing the blocks of bits are different from each other. The method further includes reading a block of bits in the interlacing table according to a memory addresses access sequence, and also writing bits to a consecutive block of bits according to the memory addresses access sequence during the reading.

Abstract translation: 用于交织数字数据以减少传输错误的方法包括将数字数据流划分成连续的比特块，并且通过写入交织表来交织每个比特块。 交错表以行和列的存储器地址的形式排列，其中多个行和列对应于预定的交织参数。 到用于交错位块的存储器地址的访问序列彼此不同。 该方法还包括根据存储器地址访问序列读取交织表中的位块，并且还在读取期间根据存储器地址访问顺序将位写入连续的位块。

公开(公告)号：US20030223289A1

公开(公告)日：2003-12-04

申请号：US10420533

申请日：2003-04-22

Applicant: STMicroelectronics SA

Inventor： Filipe Ganivet ,  Francesco La Rosa ,  Thierry Giovinazzi

IPC: G11C029/00

CPC classification number: G11C16/30

Abstract: An electrically erasable and programmable memory includes an array of memory cells, and a distribution line linked to a receiving terminal of an external supply voltage and to a booster circuit. The distribution line provides an internal supply voltage. The distribution line is also linked to the receiving terminal through a diode or a diode circuit simulating operation of a diode. The memory includes a regulator for triggering the booster circuit when the internal supply voltage becomes lower than a threshold so as to maintain the internal supply voltage close to the threshold when the external supply voltage is too low, at least during the reading of memory cells. The diode or the diode circuit is blocked when the external supply voltage is too low.

Abstract translation: 电可擦除和可编程存储器包括存储器单元的阵列，以及连接到外部电源电压的接收端的分配线和升压电路。 配电线路提供内部电源电压。 分配线还通过模拟二极管的操作的二极管或二极管电路与接收端相连。 存储器包括用于当内部电源电压变得低于阈值时触发升压电路的稳压器，以便至少在读取存储器单元期间，当外部电源电压太低时，内部电源电压保持接近阈值。 当外部电源电压太低时，二极管或二极管电路被阻塞。

公开(公告)号：US20030219126A1

公开(公告)日：2003-11-27

申请号：US10388324

申请日：2003-03-12

Applicant: STMicroelectronics SA

Inventor： Sylvie Wuidart

IPC: H04N007/167

CPC classification number: H04K3/41 ,  G06F21/755 ,  G06K19/07363 ,  H01L23/585 ,  H01L24/06 ,  H01L2924/12035 ,  H01L2924/13091 ,  H01L2924/14 ,  H04K3/60 ,  H04K3/825 ,  H04K2203/20 ,  H01L2924/00

Abstract: A method for scrambling current consumption of an integrated circuit, at least during execution of a confidential operation by the integrated circuit that includes reading confidential data stored therein and/or the calculation of an encryption code is provided. The charge pump is activated to generate current consumption fluctuations on the electrical power supply line of the integrated circuit, at an intensity great enough to mask the current consumption variations associated with the execution of the confidential operation.

Abstract translation: 提供一种用于加扰集成电路的电流消耗的方法，至少在由包括读取存储在其中的机密数据和/或加密代码的计算的集成电路执行机密操作期间。 电荷泵被激活以在集成电路的电源线上产生电流消耗波动，强度足以掩盖与执行机密操作相关联的当前消耗变化。

公开(公告)号：US20030218924A1

公开(公告)日：2003-11-27

申请号：US10406632

申请日：2003-04-03

Applicant: STMicroelectronics SA

Inventor： Benjamin Duval ,  Fabrice Marinet

IPC: G11C029/00

CPC classification number: G11C17/18

Abstract: A method of programming a row of antifuse memory cells includes breaking down at least N antifuse elements in the memory cells. The breakdown includes the application of a breakdown voltage to the anode of each antifuse element. The antifuse elements are broken down sequentially by groups of P antifuse elements, with P being less than N and at least equal to 1. The antifuse elements of a same group simultaneously receive the breakdown voltage. The breakdown of a next group of antifuse elements immediately takes place after the breakdown of a previous group of antifuse elements.

Abstract translation: 一种编程反熔丝存储单元的行的方法包括在存储单元中分解至少N个反熔丝元件。 击穿包括向每个反熔丝元件的阳极施加击穿电压。 反熔丝元件依次由P个反熔丝元件分组，其中P小于N并且至少等于1.同一组的反熔丝元件同时接收击穿电压。 下一组反熔丝元件的故障立即发生在上一组反熔丝元件击穿之后。

公开(公告)号：US20240015945A1

公开(公告)日：2024-01-11

申请号：US18347435

申请日：2023-07-05

Applicant: STMicroelectronics SA ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics International N.V.

Inventor： Olivier Weber ,  Kedar Janardan Dhori ,  Promod Kumar ,  Shafquat Jahan Ahmed ,  Christophe Lecocq ,  Pascal Urard

IPC: H10B10/00 ,  G11C11/417

CPC classification number: H10B10/12 ,  H10B10/18 ,  G11C11/417

Abstract: In one embodiment, a semiconductor device includes a carrier substrate, a buried dielectric region overlying the carrier substrate, and a semiconductor film separated from the carrier substrate by the buried dielectric region. NMOS transistors and PMOS transistors are disposed at a surface of the semiconductor film and coupled together to form a static random access memory (SRAM) cell. The NMOS transistors and the PMOS transistors each include a gate dielectric layer having a thickness greater than three nanometers and an active region in the semiconductor film. The active region of the PMOS transistors are formed from a silicon-germanium alloy.

公开(公告)号：US11867570B2

公开(公告)日：2024-01-09

申请号：US17192438

申请日：2021-03-04

Applicant: STMicroelectronics SA

Inventor： Philippe Galy ,  Renan Lethiecq

IPC: G01K7/01 ,  G01K7/22 ,  G01K7/25 ,  H01L27/12 ,  H01C7/04 ,  G05F3/24 ,  H01C7/00 ,  H01L29/10 ,  H01L29/78

CPC classification number: G01K7/01 ,  G01K7/015 ,  G01K7/22 ,  G01K7/226 ,  G01K7/25 ,  G05F3/245 ,  H01C7/008 ,  H01C7/04 ,  H01L27/1203 ,  H01L29/1095 ,  H01L29/7831

Abstract: An electronic device includes a module that delivers a positive temperature coefficient output voltage at an output terminal. A thermistor includes a first MOS transistor operating in weak inversion mode and having a negative temperature coefficient drain-source resistance and whose source is coupled to the output terminal. A current source coupled to the output terminal imposes the drain-source current of the first transistor.

公开(公告)号：US20230393250A1

公开(公告)日：2023-12-07

申请号：US18320849

申请日：2023-05-19

Applicant: STMICROELECTRONICS SA ,  STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Jeremie TEYSSIER ,  Antoine DROUOT ,  Thibault AUGEY ,  Valerie PENA-LAROCHE

IPC: G01S7/4912 ,  G01S7/481 ,  G01S17/894 ,  G01S7/4915

CPC classification number: G01S7/4918 ,  G01S7/4816 ,  G01S17/894 ,  G01S7/4915

Abstract: An indirect time-of-flight measurement sensor includes a photosensitive pixel array configured to acquire a succession of images of a scene during a given exposure time. The sensor includes a control unit configured to control the acquisition of the succession of images by the pixel array and to define an exposure time for this acquisition based on a pixel saturation rate of the array, distances between the sensor and elements of the scene, and a standard deviation of the distances between the sensor and the elements of the scene.

公开(公告)号：US11837647B2

公开(公告)日：2023-12-05

申请号：US17685780

申请日：2022-03-03

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Alexis Gauthier ,  Pascal Chevalier

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/08 ,  H01L29/732 ,  H01L21/265

CPC classification number: H01L29/66272 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/732 ,  H01L21/26513

Abstract: A bipolar transistor includes a collector. The collector is formed by: a first portion of the collector which extends under an insulating trench, and a second portion of the collector which crosses through the insulating trench. The first and second portions of the collector are in physical contact.

公开(公告)号：US20230318658A1

公开(公告)日：2023-10-05

申请号：US18174236

申请日：2023-02-24

Applicant: STMICROELECTRONICS SA ,  STIMICROELECTRONICS (GRENOBLE) SAS

Inventor： Gregoire Montjaux ,  Marc Houdebine

IPC: H04B5/00 ,  H04L7/033 ,  H03L7/099

CPC classification number: H04B5/0031 ,  H03L7/0992 ,  H03L7/0994 ,  H04L7/033

Abstract: A device is configured to receive a first carrier signal, and deliver a second carrier signal, and has a phase-locked loop including a first domain including an oscillator configured to generate a signal at a given frequency, and a circuit configured to generate information representative of the frequency of the signal generated by the oscillator, and to generate the second carrier signal and a clock signal, the first domain being clocked by the first carrier signal, a second domain, clocked by the clock signal, including a circuit configured to compare the frequency of the signal generated by the oscillator with the frequency of the first carrier signal and to control the oscillator, a matching circuit configured to transfer information representative of the frequency of the signal generated by the oscillator from the first domain to the second domain.