公开(公告)号：US11646094B2

公开(公告)日：2023-05-09

申请号：US17840765

申请日：2022-06-15

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G06F11/10

CPC classification number: G11C29/42 ,  G06F11/1012 ,  G06F11/1016 ,  G06F11/1032 ,  G06F11/1048 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401

Abstract: A memory controller generates error codes associates with write data and a write address and provides the error codes over a dedicated error detection code link to a memory device during a write operation. The memory device performs error detection, and in some cases correction, on the received write data and write address based on the error codes. If no uncorrectable errors are detected, the memory device furthermore stores the error codes in association with the write data. On a read operation, the memory device outputs the error codes over the error detection code link to the memory controller together with the read data. The memory controller performs error detection, and in some cases correction, on the received read data based on the error codes.

公开(公告)号：US11625346B2

公开(公告)日：2023-04-11

申请号：US17715379

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kenneth L. Wright

IPC: G06F11/00 ,  G06F13/16 ,  G06F11/07 ,  G06F13/40 ,  G06F11/20 ,  G06F11/16 ,  G06F11/10

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

公开(公告)号：US11621030B2

公开(公告)日：2023-04-04

申请号：US17568656

申请日：2022-01-04

Applicant: Rambus Inc.

Inventor： Wayne F. Ellis ,  Wayne S. Richardson ,  Akash Bansal ,  Frederick A. Ware ,  Lawrence Lai ,  Kishore Ven Kasamsetty

IPC: G11C11/34 ,  G11C11/406 ,  G11C7/02 ,  G11C7/20 ,  G11C11/4072 ,  G11C29/02 ,  G06F1/3234 ,  G11C11/4074

Abstract: In one embodiment, a memory device includes a memory core and input receivers to receive commands and data. The memory device also includes a register to store a value that indicates whether a subset of the input receivers are powered down in response to a control signal. A memory controller transmits commands and data to the memory device. The memory controller also transmits the value to indicate whether a subset of the input receivers of the memory device are powered down in response to the control signal. In addition, in response to a self-fresh command, the memory device defers entry into a self-refresh operation until receipt of the control signal that is received after receiving the self-refresh command.

公开(公告)号：US20230101128A1

公开(公告)日：2023-03-30

申请号：US17954086

申请日：2022-09-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware

IPC: G11C7/10 ,  G11C8/18

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory controller is disclosed. The IC memory controller includes a first controller command/address (C/A) interface to transmit first and second read commands for first and second read data to a first memory C/A interface of a first bank group of memory. A second command/address (C/A) interface transmits third and fourth read commands for third and fourth read data to a second memory C/A interface of a second bank group of memory. Receiver circuitry receives the first and second read data via a first data link interface and the third and fourth read data via the second data link interface. For a first operating mode, the first and second read data are received after respective first delays following transmission of the first and second read commands and at a first serialization ratio. For a second operating mode, the first and second read data are received after respective second and third delays following transmission of the first and second read commands. The second and third delays are different from the first delays and from each other. The first and second data are received at a second serialization ratio that is different than the first serialization ratio.

公开(公告)号：US20230100348A1

公开(公告)日：2023-03-30

申请号：US17945616

申请日：2022-09-15

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Frederick A. Ware

IPC: G06F12/14 ,  G06F3/06 ,  G06F13/16 ,  G06F12/02

Abstract: A multi-rank memory system in which calibration operations are performed between a memory controller and one rank of memory while data is transferred between the controller and other ranks of memory. A memory controller performs a calibration operation that calibrates parameters pertaining to transmission of data via a first data bus between the memory controller and a memory device in a first rank of memory. While the controller performs the calibration operation, the controller also transfers data with a memory device in a second rank of memory via a second data bus.

公开(公告)号：US11609870B2

公开(公告)日：2023-03-21

申请号：US17296532

申请日：2019-11-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Christopher Haywood

IPC: G06F13/16 ,  G06F13/40 ,  G11C7/10 ,  G11C5/04 ,  G11C11/4093 ,  G11C11/4096

Abstract: In a modular memory system, a memory control component, first and second memory sockets and data buffer components are all mounted to the printed circuit board. The first and second memory sockets have electrical contacts to electrically engage counterpart electrical contacts of memory modules to be inserted therein, and each of the data buffer components includes a primary data interface electrically coupled to the memory control component, and first and second secondary data interfaces electrically coupled to subsets of the electrical contacts within the first and second memory sockets, respectively.

公开(公告)号：US20230052220A1

公开(公告)日：2023-02-16

申请号：US17892291

申请日：2022-08-22

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Carl W. Werner

IPC: G11C7/04 ,  G06F1/12 ,  G11C7/22

Abstract: In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

公开(公告)号：US11573849B2

公开(公告)日：2023-02-07

申请号：US17236445

申请日：2021-04-21

Applicant: Rambus Inc.

Inventor： Thomas J. Giovannini ,  Catherine Chen ,  Scott C. Best ,  John Eric Linstadt ,  Frederick A. Ware

IPC: G06F11/07 ,  G11C29/44 ,  G06F13/00 ,  G11C5/04 ,  G11C7/20 ,  G11C8/12 ,  G11C29/26

Abstract: During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.

公开(公告)号：US11556164B2

公开(公告)日：2023-01-17

申请号：US17117388

申请日：2020-12-10

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Robert E. Palmer ,  John W. Poulton ,  Andrew M. Fuller

IPC: G06F1/3237 ,  G11C7/04 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G06F1/12 ,  G06F1/3225 ,  G06F1/324 ,  G06F3/06 ,  G06F1/32 ,  G06F9/38 ,  G06F12/0855 ,  G06F13/36

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

公开(公告)号：US20230009384A1

公开(公告)日：2023-01-12

申请号：US17852165

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/06 ,  H01L25/065

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.