TRIAZINE 11-BETA HYDROXYSTEROID DEHYDROGENASE TYPE 1 INHIBITORS
    531.
    发明申请
    TRIAZINE 11-BETA HYDROXYSTEROID DEHYDROGENASE TYPE 1 INHIBITORS 有权
    TRIAZINE 11-BETA HYDROOSTEROID DEHYDROGENASE TYPE 1 INHIBITORS

    公开(公告)号:US20070207985A1

    公开(公告)日:2007-09-06

    申请号:US11679898

    申请日:2007-02-28

    CPC classification number: C07D253/10 C07D253/07

    Abstract: Novel compounds are provided which are 11-beta-hydroxysteroid dehydrogenase type I inhibitors. 11-beta-hydroxysteroid dehydrogenase type I inhibitors are useful in treating, preventing, or slowing the progression of diseases requiring 11-beta-hydroxysteroid dehydrogenase type I inhibitor therapy. These novel compounds have the structure: or stereoisomers or prodrugs or pharmaceutically acceptable salts thereof, wherein R1, R2 and R3 are defined herein.

    Abstract translation: 提供了新的化合物,其为11-β-羟基类固醇脱氢酶I型抑制剂。 11-β-羟基类固醇脱氢酶I型抑制剂可用于治疗,预防或减缓需要11-β-羟基类固醇脱氢酶I型抑制剂治疗的疾病进展。 这些新化合物具有以下结构:其立体异构体或前药或其药学上可接受的盐,其中R 1,R 2和R 3 3定义在本文中 。

    Stochastic analysis process optimization for integrated circuit design and manufacture
    532.
    发明授权
    Stochastic analysis process optimization for integrated circuit design and manufacture 失效
    集成电路设计制造的随机分析过程优化

    公开(公告)号:US07243320B2

    公开(公告)日:2007-07-10

    申请号:US11301999

    申请日:2005-12-12

    CPC classification number: G06F17/5022 G06F2217/08

    Abstract: An Integrated Circuit Design tool incorporating a Stochastic Analysis Process (“SAP”) is described. The SAP can be applied on many levels of circuit components including transistor devices, logic gate devices, and System-on-Chip or chip designs. The SAP replaces a large number of traditional Monte Carlo simulations with operations using a small number of sampling points or corners. The SAP is a hierarchical approach using a model fitting process to generate a model that can be used with any number of performance memos to generate performance variation predictions along with corresponding statistical information (e.g., mean, three-sigma probability, etc.). The SAP provides an efficient way of modeling the circuit or system variation due to global parameters such as device dimensions, interconnect wiring variations, economic variations, and manufacturing variations.

    Abstract translation: 描述了结合随机分析过程(“SAP”)的集成电路设计工具。 SAP可以应用于许多级别的电路组件,包括晶体管器件,逻辑门器件和片上系统或芯片设计。 SAP使用少量采样点或角落替换大量传统的蒙特卡罗模拟,并进行操作。 SAP是使用模型拟合过程生成可以与任何数量的性能记录一起使用以产生性能变化预测以及相应的统计信息(例如,平均三西格玛概率等)的分层方法。 SAP提供了一种有效的方式来对由于全局参数(如器件尺寸,互连布线变化,经济变化和制造变化)引起的电路或系统变化进行建模。

    POWER SAVING APPARATUS AND METHOD
    534.
    发明申请
    POWER SAVING APPARATUS AND METHOD 失效
    节电装置和方法

    公开(公告)号:US20060271800A1

    公开(公告)日:2006-11-30

    申请号:US11308748

    申请日:2006-04-28

    CPC classification number: G06F1/3228

    Abstract: A power saving apparatus (20) is interposed between a power supply unit (10) and an electronic device (30). The power saving apparatus includes a switching component (210), a controlling circuit (230) controllable by the electronic device, and a switching circuit (220) controllable by the controlling circuit and the switching component. The controlling circuit receives an “idle” signal from the electronic device and controls the switching circuit to cut off the power supply to the electronic device according to the “idle” signal. The switching component produces an “awakening” signal to control the switching circuit to resume the power supply to the electronic device. A related power saving method is also introduced.

    Abstract translation: 省电装置(20)插入在电源单元(10)和电子设备(30)之间。 省电装置包括开关元件(210),由电子设备控制的控制电路(230)以及可由控制电路和开关元件控制的开关电路(220)。 控制电路从电子设备接收“空闲”信号,并根据“空闲”信号控制切换电路切断电子设备的电源。 开关组件产生“唤醒”信号以控制开关电路以恢复对电子设备的电力供应。 还介绍了一种相关的省电方法。

    Carbon nanotube interconnect
    538.
    发明授权
    Carbon nanotube interconnect 失效
    碳纳米管互连

    公开(公告)号:US07094679B1

    公开(公告)日:2006-08-22

    申请号:US10390254

    申请日:2003-03-11

    Abstract: Method and system for fabricating an electrical interconnect capable of supporting very high current densities (106–1010 Amps/cm2), using an array of one or more carbon nanotubes (CNTs). The CNT array is grown in a selected spaced apart pattern, preferably with multi-wall CNTs, and a selected insulating material, such as SiOw or SiuNv, is deposited using CVD to encapsulate each CNT in the array. An exposed surface of the insulating material is planarized to provide one or more exposed electrical contacts for one or more CNTs.

    Abstract translation: 用于制造能够支持非常高的电流密度(10 -6至10 10 Amps / cm 2)的电互连的方法和系统,使用 一个或多个碳纳米管(CNT)的阵列。 CNT阵列以选择的间隔开的图案生长,优选地使用多壁CNT,并且选择的绝缘材料,例如SiO 2或Si N 使用CVD沉积每个CNT以阵列中的每一个CNT。 绝缘材料的暴露表面被平坦化以为一个或多个CNT提供一个或多个暴露的电接触。

    Insulator coating and method for forming same
    540.
    发明申请
    Insulator coating and method for forming same 有权
    绝缘子涂层及其形成方法

    公开(公告)号:US20060081394A1

    公开(公告)日:2006-04-20

    申请号:US10966963

    申请日:2004-10-15

    Abstract: The present invention is a method of applying Lotus Effect materials as a (superhydrophobicity) protective coating for external electrical insulation system applications, as well as the method of fabricating/preparing Lotus Effect coatings. Selected inorganic or polymeric materials are applied on the insulating material surface, and stable superhydrophobic coatings can be fabricated. Various UV stabilizers and UV absorbers can be incorporated into the coating system to enhance the coating's UV stability.

    Abstract translation: 本发明是将莲花效应材料应用于外部电绝缘系统应用的(超疏水性)保护涂层的方法以及制备/制备莲花效应涂层的方法。 选择的无机或聚合物材料被施加在绝缘材料表面上,并且可以制造稳定的超疏水涂层。 可以将各种UV稳定剂和UV吸收剂掺入涂料体系中以增强涂料的UV稳定性。

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