公开(公告)号：US20240281150A1

公开(公告)日：2024-08-22

申请号：US18650966

申请日：2024-04-30

Applicant: Intel Corporation

Inventor： Yi ZENG ,  Kaushik BALASUBRAMANIAN ,  Eti BAYEVSKY ,  Yuli BARCOHEN ,  Lukasz GOLAWSKI ,  Yaniv NISSIM

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0679

Abstract: Examples described herein relate to an interface to a serial connection and circuitry to: prior to issuance of a read request to a device, issue a command to the device to identify data to be requested to be read and based on an indicator that the identified data is available to be read, send the read request for the identified data via the interface to the device. The command can include an operational code, a starting address, and length.

公开(公告)号：US20240280987A1

公开(公告)日：2024-08-22

申请号：US18595649

申请日：2024-03-05

Applicant: Intel Corporation

Inventor： Abhishek R. Appu ,  Altug Koker ,  Joydeep Ray ,  Balaji Vembu ,  John C. Weast ,  Mike B. Macpherson ,  Dukhwan Kim ,  Linda L. Hurd ,  Sanjeev Jahagirdar ,  Vasanth Ranganathan

IPC: G05D1/00 ,  G06F9/46 ,  G06F9/48 ,  G06F9/52 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06T1/20

CPC classification number: G05D1/0088 ,  G06F9/4881 ,  G06F9/522 ,  G06N3/044 ,  G06N3/045 ,  G06N3/063 ,  G06N3/084 ,  G06F9/46 ,  G06T1/20

Abstract: A mechanism is described for facilitating barriers and synchronization for machine learning at autonomous machines. A method of embodiments, as described herein, includes detecting thread groups relating to machine learning associated with one or more processing devices. The method may further include facilitating barrier synchronization of the thread groups across multiple dies such that each thread in a thread group is scheduled across a set of compute elements associated with the multiple dies, where each die represents a processing device of the one or more processing devices, the processing device including a graphics processor.

公开(公告)号：US12069581B2

公开(公告)日：2024-08-20

申请号：US17353843

申请日：2021-06-22

Applicant: Intel Corporation

Inventor： Walid El Hajj ,  Manuel Blazquez De Pineda ,  Nawfal Asrih ,  Mythili Hegde ,  John Michael Roman ,  Robert Paxman ,  Zhen Yao

IPC: H04W52/08 ,  H04B17/10 ,  H04W28/18 ,  H04W52/14

CPC classification number: H04W52/143 ,  H04B17/102 ,  H04W28/18 ,  H04W52/08

Abstract: A wireless communication device includes one or more processors, configured to determine one or more first transmission power measurements within a first transmission power measurement sampling period; calculate a first transmission power factor, the first transmission power factor representing a central tendency of the one or more first transmission power measurements from the first power measurement sampling period; determine a second power measurement during a second transmission power measurement sampling period; and calculate a second transmission power factor, wherein the second transmission power factor is a central tendency of at least one of the one or more first power measurements and the second power measurement.

公开(公告)号：US12068525B2

公开(公告)日：2024-08-20

申请号：US17938768

申请日：2022-10-07

Applicant: Intel Corporation

Inventor： Sidharth Dalmia ,  Trang Thai

IPC: H01Q1/22 ,  H01L23/66 ,  H01Q9/04 ,  H01Q21/06

CPC classification number: H01Q1/2283 ,  H01L23/66 ,  H01Q9/0407 ,  H01Q21/065 ,  H01L2223/6677 ,  H01L2924/1421 ,  H01L2924/15153 ,  H01L2924/15311

Abstract: Disclosed herein are antenna boards, integrated circuit (IC) packages, antenna modules, and communication devices. For example, in some embodiments, an antenna module may include: an IC package having a die and a package substrate, and the package substrate has a recess therein; and an antenna patch, coupled to the package substrate, such that the antenna patch is over or at least partially in the recess.

公开(公告)号：US12068206B2

公开(公告)日：2024-08-20

申请号：US17030449

申请日：2020-09-24

Applicant: Intel Corporation

Inventor： Varun Mishra ,  Stephen M. Cea ,  Cory E. Weber ,  Jack T. Kavalieros ,  Tahir Ghani

IPC: H01L23/00 ,  H01L21/84 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H10B51/10 ,  H10B51/30

CPC classification number: H01L21/845 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/78391 ,  H01L29/7853 ,  H10B51/10 ,  H10B51/30

Abstract: Embodiments of the present disclosure are based on extending a nanocomb transistor architecture to implement gate all around, meaning that a gate enclosure of at least a gate dielectric material, or both a gate dielectric material and a gate electrode material, is provided on all sides of each nanoribbon of a vertical stack of lateral nanoribbons of a nanocomb transistor arrangement. In particular, extension of a nanocomb transistor architecture to implement gate all around, proposed herein, involves use of two dielectric wall materials which are etch-selective with respect to one another, instead of using only a single dielectric wall material used to implement conventional nanocomb transistor arrangements. Nanocomb-based transistor arrangements implementing gate all around as described herein may provide improvements in terms of the short-channel effects of conventional nanocomb transistor arrangements.

公开(公告)号：US12067428B2

公开(公告)日：2024-08-20

申请号：US17128525

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Stav Gurtovoy ,  Mateusz Maria Przybylski ,  Michael Apodaca ,  Manjunath D S

IPC: G06F9/52 ,  G06F9/48 ,  G06T1/20

CPC classification number: G06F9/52 ,  G06F9/4881 ,  G06F9/522 ,  G06T1/20

Abstract: An apparatus to facilitate thread synchronization is disclosed. The apparatus comprises one or more processors to execute a producer thread to generate a plurality of commands, execute a consumer thread to process the plurality of commands and synchronize the producer thread with the consumer thread, including updating a producer fence value upon generation of in-order commands, updating a consumer fence value upon processing of the in-order commands and performing a synchronization operation based on the consumer fence value, wherein the producer fence value and the consumer fence value each correspond to an order position of an in-order command.

公开(公告)号：US12067394B2

公开(公告)日：2024-08-20

申请号：US18170696

申请日：2023-02-17

Applicant: Intel Corporation

Inventor： Shuai Mu ,  Cristina S. Anderson ,  Subramaniam Maiyuran

IPC: G06F9/30 ,  G06F7/544 ,  G06T1/20

CPC classification number: G06F9/3001 ,  G06F7/5443 ,  G06T1/20

Abstract: Embodiments are directed to systems and methods for reuse of FMA execution unit hardware logic to provide native support for execution of get exponent, get mantissa, and/or scale instructions within a GPU. These new instructions may be used to implement branch-free emulation algorithms for mathematical functions and analytic functions (e.g., transcendental functions) by detecting and handling various special case inputs within a pre-processing stage of the FMA execution unit, which allows the main dataflow of the FMA execution unit to be bypassed for such special cases. Since special cases are handled by the FMA execution unit, library functions emulating various functions, including, but not limited to logarithm, exponential, and division operations may be implemented with significantly fewer lines of machine-level code, thereby providing improved performance for HPC applications.

公开(公告)号：US12067338B2

公开(公告)日：2024-08-20

申请号：US17585101

申请日：2022-01-26

Applicant: Intel Corporation

Inventor： Ranjith Kumar ,  Quan Shi ,  Mark T. Bohr ,  Andrew W. Yeoh ,  Sourav Chakravarty ,  Barbara A. Chappell ,  M. Clair Webb

IPC: G06F30/392 ,  G06F30/20 ,  G06F30/337 ,  G06F30/347 ,  G06F30/373 ,  G06F30/3947 ,  H01L27/02 ,  H01L27/092 ,  H01L27/118 ,  H01L27/00 ,  H01L27/11

CPC classification number: G06F30/392 ,  G06F30/337 ,  G06F30/347 ,  H01L27/0207 ,  H01L27/0924 ,  H01L27/11807 ,  G06F30/20 ,  G06F30/373 ,  G06F30/3947 ,  H01L2027/11875

Abstract: Multi version library cell handling and integrated circuit structures fabricated therefrom are described. In an example, an integrated circuit structure includes a plurality of gate lines parallel along a first direction of a substrate and having a pitch along a second direction orthogonal to the first direction. A first version of a cell type is over a first portion of the plurality of gate lines, the first version of the cell type including a first plurality of interconnect lines having a second pitch along the second direction, the second pitch less than the first pitch.

公开(公告)号：US12066945B2

公开(公告)日：2024-08-20

申请号：US17130698

申请日：2020-12-22

Applicant: Intel Corporation

Inventor： Prathmesh Kallurkar ,  Anant Vithal Nori ,  Sreenivas Subramoney

IPC: G06F12/084 ,  G06F9/50 ,  G06F12/0811 ,  G06F12/0846 ,  G06F12/0871

CPC classification number: G06F12/084 ,  G06F9/5016 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/0871

Abstract: An embodiment of an integrated circuit may comprise a core, a first level core cache memory coupled to the core, a shared core cache memory coupled to the core, a first cache controller coupled to the core and communicatively coupled to the first level core cache memory, a second cache controller coupled to the core and communicatively coupled to the shared core cache memory, and circuitry coupled to the core and communicatively coupled to the first cache controller and the second cache controller to determine if a workload has a large code footprint, and, if so determined, partition N ways of the shared core cache memory into first and second chunks of ways with the first chunk of M ways reserved for code cache lines from the workload and the second chunk of N minus M ways reserved for data cache lines from the workload, where N and M are positive integer values and N minus M is greater than zero. Other embodiments are disclosed and claimed.

公开(公告)号：US12066833B2

公开(公告)日：2024-08-20

申请号：US17322056

申请日：2021-05-17

Applicant: Intel Corporation

Inventor： Rajashree Baskaran ,  Maruti Gupta Hyde ,  Min Suet Lim ,  Van Le ,  Hebatallah Saadeldeen

IPC: G05D1/00 ,  B60W30/00 ,  G08G1/01 ,  H04W4/029 ,  H04W4/38 ,  H04W4/44

CPC classification number: G05D1/0276 ,  B60W30/00 ,  G05D1/0231 ,  G08G1/0116 ,  H04W4/029 ,  H04W4/38 ,  H04W4/44

Abstract: The present disclosure may be directed to a computer-assisted or autonomous driving (CA/AD) vehicle that receives a plurality of indications of a condition of one or more features of a plurality of locations of a roadway, respectively, encoded in a plurality of navigation signals broadcast by a plurality of transmitters as the CA/AD vehicle drives past the locations enroute to a destination. The CA/AD vehicle may then determine, based in part on the received indications, driving adjustments to be made and send indications of the driving adjustments to a driving control unit of the CA/AD vehicle.