公开(公告)号：US12027475B2

公开(公告)日：2024-07-02

申请号：US18338596

申请日：2023-06-21

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Jen-Yuan Chang ,  Chien-Chang Lee ,  Chia-Ping Lai

IPC: H01L21/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/522 ,  H01L23/58 ,  H01L25/065 ,  H01L23/00 ,  H01L25/18

CPC classification number: H01L23/585 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5222 ,  H01L25/0657 ,  H01L23/562 ,  H01L25/18 ,  H01L2225/06544

Abstract: A die includes: a semiconductor substrate; an interconnect structure disposed on the semiconductor substrate and including: inter-metal dielectric (IMD) layers; metal features embedded in the IMD layers; and a guard ring structure including concentric first and second guard rings that extend through at least a subset of the IMD layers; and a through silicon via (TSV) structure extending through the semiconductor substrate and the subset of IMD layers to electrically contact one of the metal features. The first guard ring surrounds the TSV structure; and the second guard ring surrounds the first guard ring and is configured to reduce a parasitic capacitance between the guard ring structure and the TSV structure.

公开(公告)号：US12021137B2

公开(公告)日：2024-06-25

申请号：US17578569

申请日：2022-01-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Oreste Madia

IPC: H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/66969 ,  H01L21/02496 ,  H01L21/02565 ,  H01L21/02614 ,  H01L21/44 ,  H01L29/4908 ,  H01L29/78642 ,  H01L29/7869 ,  H01L21/02381 ,  H01L21/02422 ,  H01L21/02488

Abstract: A method of forming a semiconductor device may include depositing a NiAl layer on a substrate, oxidizing the NiAl layer to form a bilayer including a NiO semiconducting material layer and an AlOx layer on the NiO semiconducting material layer, forming a semiconductor layer including the NiO semiconducting material layer, the semiconductor layer also including a channel region, and forming a gate dielectric on the channel region of the semiconductor layer.

公开(公告)号：USD1031954S1

公开(公告)日：2024-06-18

申请号：US29758033

申请日：2020-11-11

Applicant: Farhad Movahhed Sariei

Designer： Farhad Movahhed Sariei

Abstract: FIG. 1 is a top-front perspective view of the shower pan design.
FIG. 2 is a front view of the shower pan design. The back view of the shower pan design is a mirror image of the front view.
FIG. 3 is a left side view of the shower pan design. The right side view of the shower pan design is a mirror image of the left side view; and,
FIG. 4 is a top view of the shower pan design.

公开(公告)号：US12015084B2

公开(公告)日：2024-06-18

申请号：US17474760

申请日：2021-09-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Mitsuhiro Togo ,  Takashi Kobayashi ,  Sudarshan Narayanan

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/6653 ,  H01L29/66795

Abstract: A field effect transistor includes at least one line trench extending downward from a top surface of a channel region which laterally surrounds or underlies the at least one line trench, a gate dielectric contacting all surfaces of the at least one line trench and including a planar gate dielectric portion that extends over an entirety of a top surface of the channel region, a gate electrode, a source region, and a drain region.

公开(公告)号：US12014976B2

公开(公告)日：2024-06-18

申请号：US18191147

申请日：2023-03-28

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Kuo Lung Pan ,  Yu-Chia Lai ,  Teng-Yuan Lo ,  Mao-Yen Chang ,  Po-Yuan Teng ,  Chen-Hua Yu ,  Chung-Shi Liu ,  Hao-Yi Tsai ,  Tin-Hao Kuo

IPC: H01L23/495 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00 ,  H01L25/16

CPC classification number: H01L23/49822 ,  H01L21/4857 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/562 ,  H01L25/16 ,  H01L25/50

Abstract: A chip package structure includes an interposer structure that contains a package-side redistribution structure, an interposer core assembly, and a die-side redistribution structure. The interposer core assembly includes at least one silicon substrate interposer, and each of the at least one silicon substrate interposer includes a respective silicon substrate, a respective set of through-silicon via (TSV) structures vertically extending through the respective silicon substrate, a respective set of interconnect-level dielectric layers embedding a respective set of metal interconnect structures, and a respective set of metal bonding structures that are electrically connected to the die-side redistribution structure. The chip package structure includes at least two semiconductor dies that are attached to the die-side redistribution structure, and an epoxy molding compound (EMC) multi-die frame that laterally encloses the at least two semiconductor dies.

公开(公告)号：US12010842B2

公开(公告)日：2024-06-11

申请号：US17166357

申请日：2021-02-03

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Akihiro Tobioka ,  Akira Yoshida

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35

Abstract: A method includes forming a first-tier alternating stack of first insulating layers and first sacrificial material layers, forming a joint dielectric layer over the first-tier alternating stack, such that the joint dielectric layer is thicker than each of the first insulating layers and the first sacrificial material layers, forming a second-tier alternating stack of second insulating layers and second sacrificial material layers over the joint dielectric layer and the first-tier alternating stack, performing a level-shift anisotropic etch process to form a recess trench or via cavities vertically extending through the second-tier alternating stack and down to the joint dielectric layer, and performing an extension etching process to extend the recess trench or the via cavities through at least the joint dielectric level. At least one of etching time or etching power used during the extension etching process is different from that used during the level-shift anisotropic etch process.

公开(公告)号：US12005481B2

公开(公告)日：2024-06-11

申请号：US17723982

申请日：2022-04-19

Applicant: Taiwan Semiconductor Manufacturing Company Limited

Inventor： Ying-Hao Wang ,  Chien-Lung Chen ,  Chia-Han Chuang ,  Jhe-Hong Wang ,  Chien-Chi Tzeng

IPC: B08B3/02 ,  H01L21/677 ,  B05B9/03 ,  B05B13/02 ,  H01L23/367 ,  H01L25/065 ,  H01L25/18

CPC classification number: B08B3/022 ,  H01L21/67706 ,  B05B9/035 ,  B05B13/0221 ,  H01L23/3675 ,  H01L25/0652 ,  H01L25/18

Abstract: An embodiment system, configured to clean a semiconductor package assembly, may include a sprayer device including a plurality of nozzles configured to direct a pressurized cleaning fluid toward the semiconductor package assembly; a conveyor configured to move the semiconductor package assembly relative to the sprayer device along a first direction; and a dryer spatially displaced from the sprayer device and configured to direct a pressurized gas flow toward the semiconductor package assembly to remove cleaning fluid introduced by the sprayer device. Each of the plurality of nozzles may be displaced from one another along a second direction to thereby generate respective separate spray distribution patterns. Adjacent nozzles may be further displaced from one another along a third direction to thereby a reduce an overlap of adjacent spray distribution patterns relative to a configuration in which the adjacent nozzles are not displaced from one another along the third direction.

公开(公告)号：US11997065B1

公开(公告)日：2024-05-28

申请号：US18112937

申请日：2023-02-22

Applicant: CHARTER COMMUNICATIONS OPERATING, LLC

Inventor： Steven R. Monti ,  Jordan A. Dechaine

IPC: H04L61/4511 ,  H04L67/52 ,  H04L67/561

CPC classification number: H04L61/4511 ,  H04L67/52 ,  H04L67/561

Abstract: Systems and network devices configured for client-side domain name system (DNS) prioritization using time zone offset to select from configured list of DNS servers. A UE device (DNS client) may determine its current time zone, and query a locally stored domain name system (DNS) server list to select a regional DNS server based on its current time zone. The UE device may send DNS requests for resource addresses to the selected regional DNS server. In response, the UE device may receive DNS response messages that priorities resource addresses based on their geographic proximity to the current time zone of the UE device.

公开(公告)号：US11996462B2

公开(公告)日：2024-05-28

申请号：US17097841

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati Prasad ,  Joyeeta Nag ,  Seung-Yeul Yang ,  Adarsh Rajashekhar ,  Raghuveer S. Makala

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L21/31155 ,  H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US11996153B2

公开(公告)日：2024-05-28

申请号：US17556298

申请日：2021-12-20

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： James Kai ,  Yuki Mizutani ,  Hisakazu Otoi ,  Masaaki Higashitani ,  Hiroyuki Ogawa

IPC: G11C16/08 ,  G11C8/14 ,  G11C16/04 ,  H01L23/48 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C16/0483 ,  G11C8/14 ,  H01L23/481 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A memory die includes an alternating stack of insulating layers and electrically conductive layers through which memory opening fill structures vertically extend. The memory die includes at least three memory array regions interlaced with at least two contact regions, or at least three contact regions interlaced with at least two memory array regions in the same memory plane. A logic die including at least two word line driver regions can be bonded to the memory die. The interlacing of the contact regions and the memory array regions can reduce lateral offset of boundaries of the word line driver regions from boundaries of the contact regions.