公开(公告)号：US20050001670A1

公开(公告)日：2005-01-06

申请号：US10884684

申请日：2004-07-02

申请人： Kwang-hyun Kim ,  Chan-Kyung Kim

发明人： Kwang-hyun Kim ,  Chan-Kyung Kim

IPC分类号： G01K7/00 ,  G01K7/01 ,  H01L21/66 ,  H03K17/08 ,  H03K3/42

CPC分类号： G01K7/01 ,  H03K2017/0806

摘要： A temperature sensing circuit and method are provided. An example temperature sensing circuit includes a temperature sensing unit that outputs a temperature signal indicating whether the temperature in the semiconductor device is higher or lower than a reference temperature in response to a first current control signal or a second current control signal by using a first current level that is increased when the temperature rises and a second current level that is reduced when the temperature rises. The temperature sensing unit also includes a storage unit that stores and outputs the temperature signal, and a controller that changes the first current level or the second current level in response to the temperature signal output from the storage unit and generates the first current control signal or the second current control signal used to control the reference temperature.

摘要翻译： 提供了温度检测电路和方法。 一个示例性温度感测电路包括温度感测单元，其通过使用第一电流输出指示半导体器件中的温度是响应于第一电流控制信号还是第二电流控制信号而高于或低于参考温度的温度信号 当温度升高时增加的电平和当温度升高时降低的第二电流水平。 温度检测单元还包括存储并输出温度信号的存储单元，以及响应于从存储单元输出的温度信号而改变第一电流电平或第二电流电平的控制器，并且产生第一电流控制信号或 用于控制参考温度的第二电流控制信号。

公开(公告)号：US09330743B2

公开(公告)日：2016-05-03

申请号：US14677991

申请日：2015-04-03

申请人： Chan-Kyung Kim ,  Kee-Won Kwon ,  Su-A Kim ,  Chul-Woo Park ,  Jae-Youn Youn

发明人： Chan-Kyung Kim ,  Kee-Won Kwon ,  Su-A Kim ,  Chul-Woo Park ,  Jae-Youn Youn

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C5/08 ,  G11C7/06 ,  G11C5/02 ,  G11C13/00 ,  G11C11/4091

CPC分类号： G11C11/16 ,  G11C5/025 ,  G11C5/08 ,  G11C7/065 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/4091 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

摘要： A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

摘要翻译： 电阻型存储器件的存储核心至少包括耦合到位线的第一电阻型存储单元，第一电阻转换器和位线读出放大器。 第一电阻转换器在第一节点处耦合到位线。 第一电阻转换器基于读列选择信号将第一电阻型存储单元的电阻转换成相应的电压。 位线读出放大器耦合到第一节点处的位线，并且耦合到第二节点处的互补位线。 位线检测放大器响应于感测控制信号而感测和放大位线和互补位线的电压差。

公开(公告)号：US20160027488A1

公开(公告)日：2016-01-28

申请号：US14722031

申请日：2015-05-26

申请人： Chan-Kyung KIM

发明人： Chan-Kyung KIM

IPC分类号： G11C11/16

CPC分类号： G11C11/1673 ,  G11C7/14 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1659

摘要： A resistive memory device may include first and second resistive memory cells, a reference current generator, and first and second bitline sense amplifiers. The reference current generator may be configured to apply the first and second reference currents to a first common node. A total reference current of the first reference current and the second reference current provided to the first common node may be divided into a first sensing current and a second sensing current by the first common node. The first and second sensing currents may be provided to the first and second bitline sense amplifiers by the first common node, respectively. The first and second bitline sense amplifiers may be configured to sense first data of the first resistive memory cell and second data of the second resistive memory cell based on the first and second sensing currents, respectively.

摘要翻译： 电阻式存储器件可以包括第一和第二电阻存储器单元，参考电流发生器以及第一和第二位线读出放大器。 参考电流发生器可以被配置为将第一和第二参考电流施加到第一公共节点。 提供给第一公共节点的第一参考电流和第二参考电流的总参考电流可以被第一公共节点划分为第一感测电流和第二感测电流。 第一和第二感测电流可以分别由第一公共节点提供给第一和第二位线读出放大器。 第一和第二位线读出放大器可以被配置为分别基于第一和第二感测电流来感测第一电阻存储器单元的第一数据和第二电阻存储器单元的第二数据。

公开(公告)号：US20150364187A1

公开(公告)日：2015-12-17

申请号：US14660530

申请日：2015-03-17

申请人： Chan-Kyung KIM ,  Kee-Won KWON

发明人： Chan-Kyung KIM ,  Kee-Won KWON

IPC分类号： G11C13/00

CPC分类号： G11C13/004 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C2013/0054

摘要： A resistive memory device may include a resistive cell array and an on-chip resistance measurement circuit. The resistive cell array may include a plurality of resistive memory cells. The on-chip resistance measurement circuit may be configured to generate a first current and a second current greater or less than the first current based on a cell current corresponding to a cell resistance of a first memory cell of the resistive memory cells, and to generate first and second digital signals based on the first and second current, respectively.

摘要翻译： 电阻式存储器件可以包括电阻单元阵列和片上电阻测量电路。 电阻单元阵列可以包括多个电阻存储单元。 片上电阻测量电路可以被配置为基于与电阻性存储器单元的第一存储单元的单元电阻对应的单元电流来产生大于或小于第一电流的第一电流和第二电流，并且生成 分别基于第一和第二电流的第一和第二数字信号。

公开(公告)号：US09070424B2

公开(公告)日：2015-06-30

申请号：US13538869

申请日：2012-06-29

申请人： YongSik Youn ,  Sooho Cha ,  Chan-kyung Kim

发明人： YongSik Youn ,  Sooho Cha ,  Chan-kyung Kim

IPC分类号： G11C11/00 ,  G11C7/06 ,  G11C13/00 ,  G11C11/16

CPC分类号： G11C7/065 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/0002 ,  G11C13/004 ,  G11C2013/0042

摘要： Example embodiments include a resistive type memory sense amplifier circuit including differential output terminals, first and second input terminals, a pre-charge section, and other components arranged so that current is re-used during at least a “set” or “amplification” stage of the sense amplifier circuit, thereby reducing overall current consumption of the circuit, and improving noise immunity. A voltage level of a high-impedance output terminal is caused to swing in response to a delta average current between a reference line current and a bit line current. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit. Also disclosed is a current mirror circuit, which can be used in conjunction with the disclosed sense amplifier circuit. In yet another embodiment, a sense amplifier circuit includes the capability of read/re-write operation.

摘要翻译： 示例性实施例包括电阻型存储读出放大器电路，其包括差分输出端，第一和第二输入端，预充电部分和其他组件，其被布置为使得电流在至少“设置”或“放大”阶段期间重新使用 ，从而降低电路的总体电流消耗，并提高抗噪声能力。 响应于参考线电流和位线电流之间的增量平均电流，使高阻抗输出端子的电压电平摆动。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。 还公开了电流镜电路，其可以与所公开的读出放大器电路结合使用。 在另一个实施例中，读出放大器电路包括读/写 - 写操作的能力。

公开(公告)号：US20140146600A1

公开(公告)日：2014-05-29

申请号：US14077274

申请日：2013-11-12

申请人： DONG HYUN SOHN ,  CHAN KYUNG KIM ,  YUN SANG LEE

发明人： DONG HYUN SOHN ,  CHAN KYUNG KIM ,  YUN SANG LEE

IPC分类号： G11C11/16

CPC分类号： G11C11/1697 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693

摘要： A magneto-resistive random access memory (MRAM) comprising an MRAM cell array having an MRAM cell, and a control and voltage generation unit configured to generate a back bias voltage for the MRAM cell. The control and voltage generation unit comprising a command decoder configured to generate a decoding signal in response to a command output from a memory controller, and a voltage controller and generator configured to generate the back bias voltage with a magnitude based on the decoding signal and a reset signal output from the memory controller.

摘要翻译： 包括具有MRAM单元的MRAM单元阵列的磁阻随机存取存储器（MRAM）以及被配置为产生MRAM单元的反向偏置电压的控制和电压产生单元。 所述控制和电压产生单元包括命令解码器，其被配置为响应于从存储器控制器输出的命令产生解码信号;以及电压控制器和发生器，被配置为基于所述解码信号产生具有幅度的所述反向偏置电压，以及 从存储器控制器输出的复位信号。

公开(公告)号：US08680930B2

公开(公告)日：2014-03-25

申请号：US13308923

申请日：2011-12-01

申请人： Chan-kyung Kim

发明人： Chan-kyung Kim

IPC分类号： H03K3/03

CPC分类号： H03K3/354 ,  G11C7/22 ,  G11C7/222

摘要： One embodiment of the oscillator includes a first starved inverter and a second starved inverter. An inner inverter of the second starved inverter is cross-coupled to an inner inverter of the first starved inverter. The oscillator further includes a first inverter connected to output of the inner inverter of the first starved inverter, and a second inverter connected to output of the inner inverter of the second starved inverter.

摘要翻译： 振荡器的一个实施例包括第一饥饿逆变器和第二饥饿逆变器。 第二饥饿逆变器的内逆变器与第一饥饿逆变器的内逆变器交叉耦合。 振荡器还包括连接到第一饥饿逆变器的内逆变器的输出的第一反相器和连接到第二饥饿逆变器的内逆变器的输出的第二反相器。

公开(公告)号：US20130051114A1

公开(公告)日：2013-02-28

申请号：US13562871

申请日：2012-07-31

申请人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

发明人： Chan-kyung Kim ,  Hong-sun Hwang ,  Chul-woo Park ,  Sang-beom Kang ,  Hyung-rok Oh

IPC分类号： G11C5/14 ,  G11C11/00 ,  G11C11/16 ,  G11C11/22

CPC分类号： G11C13/0033 ,  G11C7/062 ,  G11C7/067 ,  G11C7/08 ,  G11C7/14 ,  G11C11/1673 ,  G11C11/1693 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/004 ,  G11C13/0061 ,  G11C2013/0042 ,  G11C2013/0054

摘要： A non-volatile memory device including a cell array, which includes a plurality of memory cells, and a sense amplification circuit. The sense amplification circuit is configured to receive a data voltage of a memory cell, a first reference voltage and a second reference voltage during a data read operation of the memory cell, generate differential output signals based on a voltage level difference between the data voltage and the first and second reference voltages, and output the differential output signals as data read from the memory cell.

摘要翻译： 包括具有多个存储单元的单元阵列和读出放大电路的非易失性存储器件。 感测放大电路被配置为在存储单元的数据读取操作期间接收存储单元的数据电压，第一参考电压和第二参考电压，基于数据电压和数据电压之间的电压电平差产生差分输出信号 第一和第二参考电压，并将差分输出信号作为从存储单元读取的数据输出。

公开(公告)号：US08223822B2

公开(公告)日：2012-07-17

申请号：US12071069

申请日：2008-02-15

申请人： Chan-kyung Kim

发明人： Chan-kyung Kim

IPC分类号： H04B1/38

CPC分类号： H04L25/0272

摘要： A signal transceiver may include three transmission lines, a signal transmission unit, and/or a signal reception unit. The signal transmission unit may be configured encode first through third transmission data to generate first through third data and transmit the first through third data through the three transmission lines. The signal transmission unit may be configured to generate each of the first through third data at one of four or more voltage level. The signal reception unit may be configured to receive the first through third data and monitor voltage differences between the first through third data to restore the first through third data into first through third reception data.

摘要翻译： 信号收发器可以包括三个传输线，信号传输单元和/或信号接收单元。 信号发送单元可以被配置为将第一至第三传输数据编码，以产生第一至第三数据，并通过三条传输线发送第一至第三数据。 信号传输单元可以被配置为以四个或更多个电压电平中的一个产生第一至第三数据中的每一个。 信号接收单元可以被配置为接收第一至第三数据并监视第一至第三数据之间的电压差，以将第一至第三数据恢复为第一至第三接收数据。

公开(公告)号：US08000162B2

公开(公告)日：2011-08-16

申请号：US12614550

申请日：2009-11-09

申请人： Chan-Kyung Kim

发明人： Chan-Kyung Kim

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C8/18 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  H03B5/1206 ,  H03K3/0315 ,  H03L7/089 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0998

摘要： A voltage-controlled oscillator comprises a first oscillator and a second oscillator. The first oscillator may generate a plurality of intermediate clock signals at a plurality of first nodes, multiply connected to a plurality of first ring shape circuits, in response to a control voltage. The plurality of intermediate clock signals may have a different phase from each other and a same phase difference with each other. The second oscillator may generate a plurality of output clock signals at a plurality of second nodes, multiply connected to a plurality of second ring shape circuits, by changing a voltage level of the intermediate clock signals. The plurality of second ring shape circuits may pass the plurality of first nodes.

摘要翻译： 压控振荡器包括第一振荡器和第二振荡器。 响应于控制电压，第一振荡器可以在多个第一节点处产生多个中间时钟信号，多个连接到多个第一环形电路。 多个中间时钟信号可以具有彼此不同的相位和彼此相同的相位差。 第二振荡器可以通过改变中间时钟信号的电压电平，在多个第二节点处产生多个输出时钟信号，多个连接到多个第二环形电路。 多个第二环形电路可以通过多个第一节点。