公开(公告)号：US20160172028A1

公开(公告)日：2016-06-16

申请号：US14820197

申请日：2015-08-06

申请人： HYUN-KOOK PARK ,  CHI-WEON YOON ,  YEONG-TAEK LEE

发明人： HYUN-KOOK PARK ,  CHI-WEON YOON ,  YEONG-TAEK LEE

IPC分类号： G11C13/00 ,  G11C11/16

CPC分类号： G11C13/0026 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/2255 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069

摘要： A resistive memory device includes a column decoder having a first switch unit, including at least one pair of switches arranged in correspondence to each of a plurality of signal lines, and a second switch unit including a pair of switches arranged in correspondence to the at least one pair of switches of the first switch unit. A first pair of switches of the first switch unit includes a first switch and a second switch that are of the same type, and a second pair of switches of the second switch unit includes a third switch and a fourth switch that are connected to the first pair of switches. A selection voltage is provided to the first signal line by passing through the first switch, and an inhibit voltage is provided to the first signal line by selectively passing through the first switch or the second switch.

摘要翻译： 一种电阻式存储装置，包括具有第一开关单元的列解码器，该第一开关单元包括对应于多条信号线中的每一条布置的至少一对开关，以及第二开关单元，该第二开关单元包括对应于至少 第一开关单元的一对开关。 第一开关单元的第一对开关包括相同类型的第一开关和第二开关，第二开关单元的第二对开关包括第三开关和第四开关，第三开关和第四开关连接到第一开关 一对开关 通过穿过第一开关将选择电压提供给第一信号线，并且通过选择性地通过第一开关或第二开关将第一信号线提供禁止电压。

公开(公告)号：US20160148683A1

公开(公告)日：2016-05-26

申请号：US14839606

申请日：2015-08-28

申请人： CHI-WEON YOON ,  HYUN-KOOK PARK ,  YEONG-TAEK LEE ,  BO-GEUN KIM ,  YONG-KYU LEE

发明人： CHI-WEON YOON ,  HYUN-KOOK PARK ,  YEONG-TAEK LEE ,  BO-GEUN KIM ,  YONG-KYU LEE

IPC分类号： G11C13/00

CPC分类号： G11C13/0069 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C11/5607 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0028 ,  G11C13/004 ,  G11C2213/72

摘要： A memory device includes a memory cell array having multiple memory cells arranged respectively in regions where first signal lines cross second signal lines. The memory device further includes a decoder having multiple line selection switch units connected respectively to the of first signal lines. Each of the multiple line selection switch units applies a bias voltage to a first signal line corresponding to each of the multiple line selection switch units in response selectively to a first switching signal and a second switching signal, voltage levels of which are different from each other in activated states.

摘要翻译： 存储器件包括具有分别布置在第一信号线与第二信号线交叉的区域中的多个存储单元的存储单元阵列。 存储装置还包括具有分别连接到第一信号线的多个线路选择开关单元的解码器。 多个线路选择开关单元中的每一个选择性地响应于第一开关信号和彼此不同的第二开关信号的第一信号线施加偏置电压到对应于多个线路选择开关单元中的每一个的第一信号线 处于激活状态。

公开(公告)号：US08472247B2

公开(公告)日：2013-06-25

申请号：US13157344

申请日：2011-06-10

申请人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

发明人： Chi-Weon Yoon ,  Dong-Hyuk Chae ,  Sang-Wan Nam ,  Sung-Won Yun

IPC分类号： G11C16/10 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0483 ,  G11C16/3418

摘要： A non-volatile memory device comprises a memory cell array comprising memory cells arranged in rows connected to corresponding word lines and columns connected to corresponding bit lines, a page buffer that stores a program data, a read-write circuit that programs and re-programs the program data into selected memory cells of the memory cell array and reads stored data from the programmed memory cells, and a control circuit that controls the page buffer and the read-write circuit to program the selected memory cells by loaded the program data from in page buffer and to re-program the selected memory cells by re-loaded the program data in the page buffer.

摘要翻译： 一种非易失性存储器件包括存储单元阵列，该存储单元阵列包括连接到相应的字线和连接到相应位线的列的行中的存储单元，存储程序数据的页缓冲器，用于编程和重新编程的读写电路 将程序数据写入到存储单元阵列的选择的存储单元中，并从编程的存储器单元中读取存储的数据;以及控制电路，其控制页面缓冲器和读写电路，以通过从其中加载程序数据对所选存储单元进行编程 页面缓冲区，并通过重新加载页面缓冲区中的程序数据来重新编程所选择的存储单元。

公开(公告)号：US20120063235A1

公开(公告)日：2012-03-15

申请号：US13229107

申请日：2011-09-09

申请人： Chi Weon Yoon ,  Sang-Wan Nam ,  Dong Hyuk Chae

发明人： Chi Weon Yoon ,  Sang-Wan Nam ,  Dong Hyuk Chae

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/3418

摘要： A three-dimensional (3D) non-volatile memory includes a memory cell array and a merge driver configured to apply a merge voltage at the same level to a common source line and a bulk in the memory cell array.

摘要翻译： 三维（3D）非易失性存储器包括存储单元阵列和合并驱动器，其被配置为将相同电平的合并电压施加到存储单元阵列中的公共源线和体。

公开(公告)号：US07782680B2

公开(公告)日：2010-08-24

申请号：US12003589

申请日：2007-12-28

申请人： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： Kee-ho Jung ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C16/3454

摘要： A flash memory device includes a program data buffer configured to buffer program data to be programmed in a memory cell array, and a verify data buffer configured to compare verify data to confirm whether the program data is accurately programmed in the memory cell array, wherein at least a portion of the verify data buffer is selectively enabled as a verify data buffer or a program data buffer responsive to a buffer control signal.

摘要翻译： 闪速存储器件包括被配置为缓冲要在存储器单元阵列中编程的程序数据的程序数据缓冲器，以及配置为比较验证数据以确认程序数据是否被精确地编程在存储单元阵列中的校验数据缓冲器，其中， 验证数据缓冲器的至少一部分被有选择地启用为响应于缓冲器控制信号的验证数据缓冲器或程序数据缓冲器。

公开(公告)号：US07668015B2

公开(公告)日：2010-02-23

申请号：US12005366

申请日：2007-12-27

申请人： Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

发明人： Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC分类号： G11C16/04

CPC分类号： G11C11/5628

摘要： In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

摘要翻译： 在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。 根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。 搜索到的数据位被编程为响应于同时编程的位的数量。 对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

公开(公告)号：US07602650B2

公开(公告)日：2009-10-13

申请号：US11847388

申请日：2007-08-30

申请人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C11/34

CPC分类号： G11C8/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.

摘要翻译： 在一个方面，提供了一种用于闪存器件的程序方法，其包括多个存储器单元，每个存储器单元以多个数据状态中的一个被编程。 该方面的程序方法包括以第一数据状态编程所选择的存储单元，验证编程结果，以对应于低于对应于阈值电压的阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选存储单元 第一数据状态，以及验证连续编程的结果。

公开(公告)号：US07474587B2

公开(公告)日：2009-01-06

申请号：US11673996

申请日：2007-02-12

申请人： Chi-Weon Yoon

发明人： Chi-Weon Yoon

IPC分类号： G11C8/00

CPC分类号： G11C8/04 ,  G11C16/26

摘要： A flash memory device includes a memory cell array, an address buffer circuit including address buffers, each address buffer configured to store an address for a random read operation, a read circuit configured to sense data from the memory cell array in response to an address output from the address buffer circuit, an output data latch circuit configured to receive data sensed by the read circuit, and a control logic coupled to the address buffer circuit, the read circuit, and the output data latch circuit, and configured to control the output data latch circuit and the read circuit such that the output data latch circuit outputs first data read from the memory cell array substantially simultaneously as the read circuit senses second data from the memory cell array.

摘要翻译： 闪速存储器件包括存储单元阵列，包括地址缓冲器的地址缓冲器电路，每个地址缓冲器被配置为存储用于随机读取操作的地址;读取电路，被配置为响应于地址输出来检测来自存储器单元阵列的数据 从所述地址缓冲电路输出的数据锁存电路被配置为接收由所述读取电路感测的数据，以及控制逻辑，其耦合到所述地址缓冲器电路，所述读取电路和所述输出数据锁存电路，并且被配置为控制所述输出数据 锁存电路和读取电路，使得当读取电路从存储器单元阵列感测到第二数据时，输出数据锁存电路基本上同时输出从存储单元阵列读取的第一数据。

公开(公告)号：US20090003056A1

公开(公告)日：2009-01-01

申请号：US12129820

申请日：2008-05-30

申请人： Jin-Young CHUN ,  Jae-Yong JEONG ,  Chi-Weon YOON

发明人： Jin-Young CHUN ,  Jae-Yong JEONG ,  Chi-Weon YOON

IPC分类号： G11C16/06 ,  G11C16/00

CPC分类号： G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

摘要： Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.

摘要翻译： 公开了一种非易失性存储器件的非易失性存储器件和编程方法。 非易失性存储器件的编程方法包括对存储器单元执行第一编程操作，在第一编程操作之后从存储单元检索原始数据，并参考原始数据和第二验证电压进行第二编程操作 比第一编程操作的第一验证电压。

公开(公告)号：US07433244B2

公开(公告)日：2008-10-07

申请号：US11501070

申请日：2006-08-09

申请人： Chi-Weon Yoon ,  Heung-Soo Lim

发明人： Chi-Weon Yoon ,  Heung-Soo Lim

IPC分类号： G11C16/00

CPC分类号： G11C16/16 ,  G11C16/3409 ,  G11C16/345 ,  G11C16/3477

摘要： An erase operation for a flash memory device includes identifying a sector group including a plurality of sectors based on an address, simultaneously pre-programming the sectors in the sector group, simultaneously erasing the sectors the sector group, and simultaneously post-programming the sectors in the sector group.

摘要翻译： 闪存器件的擦除操作包括基于地址识别包括多个扇区的扇区组，同时对扇区组中的扇区进行预编程，同时擦除扇区组，并同时对扇区进行后编程 行业组。