公开(公告)号：US20110220974A1

公开(公告)日：2011-09-15

申请号：US12873788

申请日：2010-09-01

Applicant: Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya

Inventor： Kazuhide Abe ,  Tadahiro Sasaki ,  Atsuko Iida ,  Kazuhiko Itaya

IPC: H01L29/78

CPC classification number: H01L29/78 ,  H01L29/41758 ,  H01L29/4238 ,  H03B5/326

Abstract: According to an embodiment, the present invention provides a semiconductor device that is easily integrated with other electronic circuits and functions as an oscillator with high frequency accuracy. The semiconductor device includes: a semiconductor substrate; an element region; an element isolation region that surrounds the element region; a field effect transistor including a gate electrode that is formed on the element region, source and drain regions, and a channel region that is interposed between the source region and the drain region; gate, source, and drain terminals that are used to apply a voltage to the gate electrode, the source region, and the drain region, respectively; and an output terminal that is electrically connected to the channel region. When the threshold voltage of the field effect transistor is Vth, a gate voltage Vgs applied between the source terminal and the gate terminal and a drain voltage Vds applied between the source terminal and the drain terminal satisfy the following relationship: Vth

Abstract translation: 根据实施例，本发明提供一种与其他电子电路容易集成并且作为高频精度的振荡器起作用的半导体器件。 半导体器件包括：半导体衬底; 元素区域 围绕元件区域的元件隔离区域; 场效应晶体管，其包括形成在所述元件区域，源极和漏极区域上的栅极电极以及介于所述源极区域和所述漏极区域之间的沟道区域; 栅极，源极和漏极端子，分别用于向栅极电极，源极区域和漏极区域施加电压; 以及电连接到沟道区的输出端子。 当场效应晶体管的阈值电压为Vth时，施加在源极端子和栅极端子之间的栅极电压Vgs和施加在源极端子和漏极端子之间的漏极电压Vds满足以下关系：Vth

公开(公告)号：US07888762B2

公开(公告)日：2011-02-15

申请号：US12314955

申请日：2008-12-19

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L31/058

CPC classification number: G01J5/20 ,  G01J5/02 ,  G01J5/023

Abstract: There is provided an infrared detector including: a silicon substrate provided with a concave portion; an infrared receiver having a polysilicon layer; and a beam that supports the infrared receiver above the concave portion, and extends along a side of the infrared receiver from the infrared receiver to connect with the silicon substrate, the beam having at least two bent portions, wherein at least one of the bent portions of the beam is disposed at a position on a side opposite to the concave portion with the polysilicon layer as a reference point.

Abstract translation: 提供一种红外检测器，包括：设置有凹部的硅基板; 具有多晶硅层的红外线接收器; 以及梁，其在所述凹部上方支撑所述红外线接收器，并且沿着所述红外线接收器的一侧从所述红外接收器延伸以与所述硅基板连接，所述梁具有至少两个弯曲部分，其中所述弯曲部分中的至少一个 的光束以与多晶硅层为基准的凹部对置的一侧的位置配置。

公开(公告)号：US07796710B2

公开(公告)日：2010-09-14

申请号：US11268615

申请日：2005-11-08

Applicant: Kazuhide Abe ,  Michihiko Nishigaki ,  Toshihiko Nagano ,  Takashi Kawakubo

Inventor： Kazuhide Abe ,  Michihiko Nishigaki ,  Toshihiko Nagano ,  Takashi Kawakubo

IPC: H04L27/22

CPC classification number: H04L27/2276

Abstract: A digital demodulator includes a resonator having a resonance frequency same as a carrier frequency to store a charge corresponding to a digital signal modulated by phase shift keying, a capacitor to store the charge of the resonator, an amplifier including an input node and an output node between which the capacitor is connected to convert a stored charge of the capacitor into a voltage signal, and a controller configured to accumulate in the resonator the charge induced by the frequency signal modulated by phase shift keying in a first control mode and configured to transfer the charge of the resonator to the capacitor in a second control mode, to output the voltage signal corresponding to the stored charge of the capacitor from the output node of the amplifier.

Abstract translation: 数字解调器包括具有与载波频率相同的谐振频率的谐振器，以存储与通过相移键控调制的数字信号相对应的电荷，存储谐振器的电荷的电容器，包括输入节点和输出节点的放大器 其间连接有电容器以将存储的电容器的电荷转换成电压信号，以及控制器，被配置为在第一控制模式中在谐振器中累积由相移键控调制的频率信号引起的电荷， 在第二控制模式下将谐振器充电到电容器，以从放大器的输出节点输出与电容器的存储电荷相对应的电压信号。

公开(公告)号：US20100006962A1

公开(公告)日：2010-01-14

申请号：US12458188

申请日：2009-07-02

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L31/02 ,  H01L21/30

CPC classification number: G01J5/02 ,  G01J5/023 ,  G01J5/024 ,  G01J5/04 ,  G01J5/046 ,  H01L21/306

Abstract: Disclosed is a method for fabrication of a porous structure that can prevent release of a protective layer from a semiconductor substrate even if a liquid chemical is used during an anodic oxidation process. The method includes forming an oxide layer on an upper face of the semiconductor substrate. The semiconductor substrate has a diffusion layer in its upper face. The method also includes forming a plurality of contact holes at desired positions of the oxide layer. The method also includes forming a wire in each of the contact holes, and forming an opening between wires to expose a surface of the diffusion layer. The method also includes forming a drain on a peripheral circumference of the opening and depositing a protective film over an entire upper part of the substrate. The protective film fills the drain. The method also includes removing most of the protective film from the opening while leaving behind a part of the protective film on the peripheral circumference of the opening and exposing a certain portion of the diffusion layer. The method also includes applying an anodic oxidation process to the exposed diffusion layer using the remaining protective film as a protective layer.

Abstract translation: 公开了一种多孔结构体的制造方法，即使在阳极氧化工序中使用液体化学物质，也能够防止半导体基板的保护层脱模。 该方法包括在半导体衬底的上表面上形成氧化物层。 半导体衬底在其上表面具有扩散层。 该方法还包括在氧化物层的期望位置形成多个接触孔。 该方法还包括在每个接触孔中形成线，并且在导线之间形成开口以暴露扩散层的表面。 该方法还包括在开口的圆周上形成漏极，并在衬底的整个上部上沉积保护膜。 保护膜填充排水管。 该方法还包括从开口中除去大部分保护膜，同时在开口的周围留下保护膜的一部分并暴露扩散层的某一部分。 该方法还包括使用剩余的保护膜作为保护层将阳极氧化工艺应用于暴露的扩散层。

公开(公告)号：US20090021140A1

公开(公告)日：2009-01-22

申请号：US12122472

申请日：2008-05-16

Applicant: Isao TAKASU ,  Yuko NOMURA ,  Tsuyoshi HIOKI ,  Isao AMEMIYA ,  Kazuhide ABE

Inventor： Isao TAKASU ,  Yuko NOMURA ,  Tsuyoshi HIOKI ,  Isao AMEMIYA ,  Kazuhide ABE

IPC: H01L21/00 ,  H01J1/62

CPC classification number: H01L33/54 ,  H01L33/46 ,  H01L33/507 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2933/0041 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a light emitting device. The method includes: mounting a light emitting chip on a substrate; forming a transparent resin portion and a phosphor layer by using a liquid droplet discharging apparatus, the transparent resin portion being formed in a shape of a dome and covering the light emitting chip to fill an exterior thereof on the substrate, a phosphor layer containing phosphor and being formed on an exterior of the transparent resin portion close to at least a top side thereof; and forming a reflecting layer at a position exterior of the transparent resin portion and the phosphor layer close to the substrate.

Abstract translation: 一种制造发光器件的方法。 该方法包括：将发光芯片安装在基板上; 通过使用液滴喷射装置形成透明树脂部分和荧光体层，所述透明树脂部分形成为圆顶形状并且覆盖所述发光芯片以将其外部填充在所述基板上，所述荧光体层包含磷光体和 形成在透明树脂部分的至少其顶侧附近的外部; 并且在透明树脂部分的外部和靠近基板的荧光体层的位置处形成反射层。

公开(公告)号：US07459827B2

公开(公告)日：2008-12-02

申请号：US11115107

申请日：2005-04-27

Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC: H01L41/08

CPC classification number: H01H57/00 ,  B81B3/0021 ,  H01G5/16 ,  H01G5/18 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/0933 ,  H01L41/094

Abstract: A piezoelectric-driven MEMS device can be fabricated reliably and consistently. The piezoelectric-driven MEMS device includes: a movable flat beam having a piezoelectric film disposed above a substrate with a recessed portion such that the piezoelectric film is bridged over the recessed portion, piezoelectric drive mechanisms disposed at both ends of the piezoelectric film and configured to drive the piezoelectric film, and a first electrode disposed at the center of the substrate-side of the piezoelectric film, and a second electrode disposed on a flat part of the recessed portion of the substrate and facing the first electrode of the movable flat beam.

Abstract translation: 可以可靠且一致地制造压电驱动的MEMS器件。 压电驱动MEMS器件包括：可移动平板光束，其具有设置在具有凹部的基板上方的压电膜，使得压电膜桥接在凹部上，压电驱动机构设置在压电膜的两端并被配置为 驱动所述压电膜，以及设置在所述压电膜的基板侧的中心的第一电极，以及设置在所述基板的所述凹部的平坦部分上并且面对所述可动平坦梁的所述第一电极的第二电极。

公开(公告)号：US20080293245A1

公开(公告)日：2008-11-27

申请号：US12170458

申请日：2008-07-10

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/2885 ,  H01L21/31116 ,  H01L21/3212 ,  H01L21/32135 ,  H01L21/32136 ,  H01L21/76801 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76865 ,  H01L21/76877 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a semiconductor substrate, a first insulating film formed on a surface of the semiconductor substrate, a first recess formed in the first insulating film, a first barrier film formed on an inner surface of the first insulating film except a top peripheral region of the first trench, a first conductive film formed in the first trench, and a covering film formed on an upper surface and a top peripheral region of the first conductive film and an upper surface of the first barrier film. The first conductive film includes copper.

Abstract translation: 半导体器件具有半导体衬底，形成在半导体衬底的表面上的第一绝缘膜，形成在第一绝缘膜中的第一凹槽，形成在除了顶部周边区域之外的第一绝缘膜的内表面上的第一阻挡膜 形成在第一沟槽中的第一导电膜和形成在第一导电膜的上表面和顶周边区域上的覆盖膜和第一阻挡膜的上表面。 第一导电膜包括铜。

公开(公告)号：US07408213B2

公开(公告)日：2008-08-05

申请号：US11393830

申请日：2006-03-31

Applicant: Kazuhide Abe

Inventor： Kazuhide Abe

IPC: H01L31/062

CPC classification number: H01L27/11507 ,  H01L27/105 ,  H01L27/11502 ,  H01L27/11509 ,  H01L28/57 ,  H01L28/65

Abstract: A ferroelectric memory device has a lower insulating film formed on a semiconductor substrate. A ferroelectric capacitor structure is formed on the lower insulating film. The ferroelectric capacitor structure is created by layering in order a lower electrode, ferroelectric layer and upper electrode. The ferroelectric memory device also has an upper insulating film which covers the ferroelectric capacitor structure. A wiring layer is formed over the upper insulating film. An aluminum oxide film of thickness 5 to 50 nm is formed so as to cover the wiring layer and upper insulating film.

Abstract translation: 铁电存储器件具有形成在半导体衬底上的下绝缘膜。 在下绝缘膜上形成铁电电容器结构。 铁电电容器结构通过按照下电极，铁电层和上电极的分层来形成。 铁电存储器件还具有覆盖铁电体电容器结构的上绝缘膜。 在上绝缘膜上形成布线层。 形成厚度为5〜50nm的氧化铝膜，以覆盖布线层和上绝缘膜。

公开(公告)号：US20080164237A1

公开(公告)日：2008-07-10

申请号：US12038568

申请日：2008-02-27

Applicant: Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

Inventor： Takashi Kawakubo ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki

IPC: H01L41/22

CPC classification number: H01H57/00 ,  B81B3/0021 ,  H01G5/16 ,  H01G5/18 ,  H01H59/0009 ,  H01H2057/006 ,  H01L41/0933 ,  H01L41/094

Abstract: A piezoelectric-driven MEMS device can be fabricated reliably and consistently. The piezoelectric-driven MEMS device includes: a movable flat beam having a piezoelectric film disposed above a substrate with a recessed portion such that the piezoelectric film is bridged over the recessed portion, piezoelectric drive mechanisms disposed at both ends of the piezoelectric film and configured to drive the piezoelectric film, and a first electrode disposed at the center of the substrate-side of the piezoelectric film, and a second electrode disposed on a flat part of the recessed portion of the substrate and facing the first electrode of the movable flat beam.

Abstract translation: 可以可靠且一致地制造压电驱动的MEMS器件。 压电驱动MEMS器件包括：可移动平板光束，其具有设置在具有凹部的基板上方的压电膜，使得压电膜桥接在凹部上，压电驱动机构设置在压电膜的两端并被配置为 驱动所述压电膜，以及设置在所述压电膜的基板侧的中心的第一电极，以及设置在所述基板的所述凹部的平坦部分上并且面对所述可动平坦梁的所述第一电极的第二电极。

公开(公告)号：US20080074005A1

公开(公告)日：2008-03-27

申请号：US11946913

申请日：2007-11-29

Applicant: Kenya SANO ,  Ryoichi Ohara ,  Naoko Yanase ,  Takaaki Yasumoto ,  Kazuhiko Itaya ,  Takashi Kawakubo ,  Hiroshi Toyoda ,  Masahiko Hasunuma ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki ,  Hironobu Shibata

Inventor： Kenya SANO ,  Ryoichi Ohara ,  Naoko Yanase ,  Takaaki Yasumoto ,  Kazuhiko Itaya ,  Takashi Kawakubo ,  Hiroshi Toyoda ,  Masahiko Hasunuma ,  Toshihiko Nagano ,  Kazuhide Abe ,  Michihiko Nishigaki ,  Hironobu Shibata

IPC: H01L41/047

CPC classification number: H03H9/02015 ,  H01H2057/006 ,  H01L41/0477 ,  H01L41/094 ,  H01L41/316 ,  H01L41/319 ,  H03H3/02 ,  H03H9/02094 ,  H03H9/173 ,  H03H9/174 ,  H03H9/175 ,  H03H9/542 ,  H03H9/582 ,  H03H9/605 ,  H03H2003/021 ,  H03H2003/023 ,  H03H2003/025 ,  Y10T29/42 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49005 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: A piezoelectric thin film device includes an amorphous metal film disposed on a substrate and a piezoelectric film disposed on the amorphous metal. One of crystal axis of the piezoelectric film is aligned in a direction perpendicular to a surface of the amorphous metal.