公开(公告)号：US07371633B2

公开(公告)日：2008-05-13

申请号：US11027256

申请日：2004-12-30

Applicant: Jong-Ho Lee ,  Nae-In Lee

Inventor： Jong-Ho Lee ,  Nae-In Lee

IPC: H01L21/8238

CPC classification number: H01L21/02175 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02192 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/7881 ,  H01L29/94

Abstract: A semiconductor device comprises a silicate interface layer and a high-k dielectric layer overlying the silicate interface layer. The high-k dielectric layer comprises metal alloy oxides.

Abstract translation: 半导体器件包括硅酸盐界面层和覆盖硅酸盐界面层的高k电介质层。 高k电介质层包括金属合金氧化物。

公开(公告)号：US20070262393A1

公开(公告)日：2007-11-15

申请号：US11797827

申请日：2007-05-08

Applicant: Il-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

Inventor： Il-Young Yoon ,  Hong-Jae Shin ,  Nae-In Lee ,  Jae-Ouk Choo ,  Ja-Eung Koo

IPC: H01L29/76 ,  H01L21/76 ,  H01L21/461 ,  H01L29/94 ,  H01L21/302 ,  H01L31/00

CPC classification number: H01L21/31053 ,  H01L21/76229

Abstract: Example embodiments provide a semiconductor device and a method of forming the same. According to the method, a capping insulation pattern may be formed to cover the top surface of a filling insulation pattern in a trench. The capping insulation pattern may have an etch selectivity according to the filling insulation pattern. As a result, the likelihood that the filling insulation layer may be etched by various cleaning processes and the process removing the buffer insulation pattern may be reduced or prevented.

Abstract translation: 示例性实施例提供半导体器件及其形成方法。 根据该方法，可以形成覆盖绝缘图案以覆盖沟槽中的填充绝缘图案的顶表面。 封盖绝缘图案可以根据填充绝缘图案具有蚀刻选择性。 结果，可以减少或防止填充绝缘层可以通过各种清洁处理蚀刻的可能性以及去除缓冲绝缘图案的过程。

公开(公告)号：US20060115993A1

公开(公告)日：2006-06-01

申请号：US11333741

申请日：2006-01-17

Applicant: Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

Inventor： Seok-Joo Doh ,  Hyung-suk Jung ,  Nae-in Lee ,  Jong-ho Lee ,  Yun-seok Kim

IPC: H01L21/31

CPC classification number: H01L21/02329 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02192 ,  H01L21/022 ,  H01L21/02323 ,  H01L21/02337 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/3143 ,  H01L21/31616 ,  H01L21/31641 ,  H01L21/31645 ,  H01L21/31662 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

Abstract: High dielectric layers formed from layers of hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide, and/or other metal oxides and silicates disposed on silicon substrates or ozone oxide layers over silicon substrates may be nitrided and post thermally treated by oxidation, annealing, or a combination of oxidation and annealing to form high dielectric layers having superior mobility and interfacial characteristics.

公开(公告)号：US06881650B2

公开(公告)日：2005-04-19

申请号：US10307351

申请日：2002-12-02

Applicant: Jung-Il Lee ,  Kazuyuki Fujihara ,  Nae-In Lee ,  Geum-Jong Bae ,  Hwa-Sung Rhee ,  Sang-su Kim

Inventor： Jung-Il Lee ,  Kazuyuki Fujihara ,  Nae-In Lee ,  Geum-Jong Bae ,  Hwa-Sung Rhee ,  Sang-su Kim

IPC: H01L21/205 ,  H01L21/02 ,  H01L21/20 ,  H01L21/30 ,  H01L21/46 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76254

Abstract: A method for forming SOI substrates including a SOI layer containing germanium and a strained silicon layer disposed on the SOI layer, comprises forming a relaxed silicon-germanium layer on a first silicon substrate using an epitaxial growth method, and forming a porous silicon-germanium layer thereon. A silicon-germanium epitaxial layer is formed on the porous silicon-germanium layer, an oxide layer is formed on a second silicon substrate, the second silicon substrate is bonded where the oxide layer is formed to the first silicon substrate where the silicon-germanium epitaxial layer is formed. Layers are removed to expose the silicon-germanium epitaxial layer and a strained silicon epitaxial layer is formed thereon. The porous silicon-germanium layer prevents lattice defects of the relaxed silicon-germanium layer from transferring to the silicon-germanium epitaxial layer. Therefore, it is possible to form the silicon-germanium layer and the strained silicon layer of the SOI layer without defects.

Abstract translation: 一种用于形成包括含有锗的SOI层和设置在SOI层上的应变硅层的SOI衬底的方法包括：使用外延生长方法在第一硅衬底上形成松弛的硅 - 锗层，并且形成多孔硅 - 锗层 上。 在多孔硅锗层上形成硅 - 锗外延层，在第二硅衬底上形成氧化物层，将形成氧化物层的第二硅衬底接合到第一硅衬底上，其中硅 - 锗外延 形成层。 去除层以暴露硅 - 锗外延层，并在其上形成应变硅外延层。 多孔硅 - 锗层防止松散的硅 - 锗层的晶格缺陷转移到硅 - 锗外延层。 因此，可以形成SOI层的硅 - 锗层和应变硅层，而没有缺陷。

公开(公告)号：US06881621B2

公开(公告)日：2005-04-19

申请号：US10713216

申请日：2003-11-17

Applicant: Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

Inventor： Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

IPC: H01L27/04 ,  H01L21/00 ,  H01L21/02 ,  H01L21/68 ,  H01L21/74 ,  H01L21/822 ,  H01L21/8238 ,  H01L21/84 ,  H01L23/62 ,  H01L27/01 ,  H01L27/02 ,  H01L27/06 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/00 ,  H01L29/72 ,  H01L31/0392

CPC classification number: H01L21/6835 ,  H01L21/743 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68363 ,  H01L2924/30105

Abstract: A method of fabricating a SOI substrate includes sequentially forming a first semiconductor layer, which may be either a porous semiconductor layer or a bubble layer, a second semiconductor layer and a buried oxide layer on a front surface of a semiconductor substrate, forming an etch stopping layer, which may be a silicon nitride layer, on a front surface of a supporting substrate; contacting the etch stopping layer with the buried oxide layer to bond the semiconductor substrate to the supporting substrate; and selectively removing the semiconductor substrate and the first semiconductor layer to expose the second semiconductor layer. The method may additionally include forming a buffer oxide layer between the supporting substrate and the etch stopping layer.

Abstract translation: 制造SOI衬底的方法包括在半导体衬底的前表面上顺序地形成可以是多孔半导体层或气泡层的第一半导体层，第二半导体层和掩埋氧化物层，形成蚀刻停止 层，其可以是氮化硅层;在支撑衬底的前表面上; 使所述蚀刻停止层与所述掩埋氧化物层接触以将所述半导体衬底接合到所述支撑衬底; 以及选择性地去除所述半导体衬底和所述第一半导体层以暴露所述第二半导体层。 该方法还可以包括在支撑衬底和蚀刻停止层之间形成缓冲氧化物层。

公开(公告)号：US06815764B2

公开(公告)日：2004-11-09

申请号：US10388631

申请日：2003-03-17

Applicant: Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

Inventor： Geum-Jong Bae ,  Nae-In Lee ,  Sang Su Kim ,  Ki Chul Kim ,  Jin-Hee Kim ,  In-Wook Cho ,  Sung-Ho Kim ,  Kwang-Wook Koh

IPC: H01L29792

CPC classification number: H01L29/792 ,  H01L29/7923 ,  Y10S438/954

Abstract: A local SONOS structure having a two-piece gate and a self-aligned ONO structure includes: a substrate; an ONO structure on the substrate; a first gate layer on and aligned with the ONO structure; a gate insulator on the substrate aside the ONO structure; and a second gate layer on the first gate layer and on the gate insulator. The first and second gate layers are electrically connected together. Together, the ONO structure and first and second gate layers define at least a 1-bit local SONOS structure. A corresponding method of manufacture includes: providing a substrate; forming an ONO structure on the substrate; forming a first gate layer on and aligned with the ONO structure; forming a gate insulator on the substrate aside the ONO structure; forming a second gate layer on the first gate layer and on the gate insulator; and electrically connecting the first and second gate layers.

Abstract translation: 具有两件式门和自对准ONO结构的本地SONOS结构包括：衬底; 基底上的ONO结构; 在ONO结构上并与ONO结构对准的第一栅极层; 衬底上的栅极绝缘体旁边的ONO结构; 以及在第一栅极层上和栅极绝缘体上的第二栅极层。 第一和第二栅极层电连接在一起。 ONO结构和第一和第二栅极层一起定义至少1位本地SONOS结构。 相应的制造方法包括：提供衬底; 在基板上形成ONO结构; 在ONO结构上形成第一栅极层并与其结合; 在衬底上形成栅极绝缘体，除了ONO结构; 在第一栅极层和栅极绝缘体上形成第二栅极层; 并且电连接第一和第二栅极层。

公开(公告)号：US06806517B2

公开(公告)日：2004-10-19

申请号：US10388427

申请日：2003-03-17

Applicant: Sang Su Kim ,  Nae-In Lee ,  Geum-Jong Bae ,  Ki Chul Kim ,  Hwa Sung Rhee

Inventor： Sang Su Kim ,  Nae-In Lee ,  Geum-Jong Bae ,  Ki Chul Kim ,  Hwa Sung Rhee

IPC: H01L2710

CPC classification number: H01L29/4232 ,  H01L21/28114 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/66833 ,  H01L29/7923

Abstract: A notched gate SONOS transistor includes: a substrate having source/drain regions; a gate insulator layer on the substrate between the source/drain regions; a notched gate structure, on the gate insulator leyer, having at least one notch; and at least one ONO wedge structure in the at least one notch, respectively, of the gate structure.

Abstract translation: 缺口门SONOS晶体管包括：具有源/漏区的衬底; 在源/漏区之间的衬底上的栅极绝缘体层; 在所述栅极绝缘体雷管上具有至少一个凹口的缺口栅极结构; 以及分别在所述栅极结构的所述至少一个凹口中的至少一个ONO楔形结构。

公开(公告)号：US06727130B2

公开(公告)日：2004-04-27

申请号：US10006093

申请日：2001-12-06

Applicant: Woo-Sik Kim ,  Nae-In Lee

Inventor： Woo-Sik Kim ,  Nae-In Lee

IPC: H01L21238

CPC classification number: H01L21/823857 ,  H01L21/823842

Abstract: A method of forming a CMOS type semiconductor device having dual gate includes forming a first gate insulation layer and a first metal-containing layer sequentially on a surface of a substrate in first and second impurity type transistor regions, removing the first metal-containing layer and the first gate insulation layer in the second impurity type transistor region, forming a second gate insulation layer and a second metal-containing layer in the second impurity type transistor region, and forming first and second electrodes in the first and second impurity type transistor regions, respectively, by patterning the first and second metal-containing layers. When first and second impurities in the transistor regions are p-type and n-type impurities, respectively, a fermi level of the first metal-containing layer has an energy level similar to the valence band of the silicon layer in the first impurity type transistor region heavily doped by a p-type impurity, and a fermi level of the second metal-containing layer has an energy level similar to the conduction band of the silicon layer in the second impurity type transistor region heavily doped by an n-type impurity.

Abstract translation: 一种形成具有双栅极的CMOS型半导体器件的方法包括：在第一和第二杂质型晶体管区域的衬底的表面上依次形成第一栅极绝缘层和第一含金属层，去除第一含金属层和 在所述第二杂质型晶体管区域中形成第一栅极绝缘层，在所述第二杂质型晶体管区域中形成第二栅极绝缘层和第二含金属层，以及在所述第一和第二杂质型晶体管区域中形成第一和第二电极， 分别通过图案化第一和第二含金属层。 当晶体管区域中的第一和第二杂质分别为p型和n型杂质时，第一含金属层的费米能级具有与第一杂质型晶体管中的硅层的价带相似的能级 由p型杂质重掺杂的区域，并且第二含金属层的费米能级具有与由n型杂质重掺杂的第二杂质型晶体管区域中的硅层的导带相似的能级。

公开(公告)号：US06670677B2

公开(公告)日：2003-12-30

申请号：US09989112

申请日：2001-11-21

Applicant: Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

Inventor： Tae-Hee Choe ,  Nae-In Lee ,  Geum-Jong Bae ,  Sang-Su Kim ,  Hwa-Sung Rhee

IPC: H01L2972

CPC classification number: H01L21/6835 ,  H01L21/743 ,  H01L21/8221 ,  H01L21/84 ,  H01L27/0251 ,  H01L27/0688 ,  H01L27/1203 ,  H01L2221/68363 ,  H01L2924/30105

Abstract: A SOI substrate having an etch stopping layer, a SOI integrated circuit fabricated on the SOI substrate, and a method of fabricating both are provided. The SOI substrate includes a supporting substrate, an etch stopping layer staked on the supporting substrate, a buried oxide layer and a semiconductor layer sequentially stacked on the etch stopping layer. The etch stopping layer preferably has an etch selectivity with respect to the buried oxide layer. A device isolation layer is preferably formed to define active regions. The device isolation, buried oxide and etch-stop layers are selectively removed to form first and second holes exposing the supporting substrate without damaging it. Semiconductor epitaxial layers grown on the exposed supporting substrate therefore have single crystalline structures without crystalline defects. Thus, when impurity regions are formed at surfaces of the epitaxial layers, a high performance PN diode having a superior leakage current characteristic may be formed.

Abstract translation: 提供了具有蚀刻停止层的SOI衬底，在SOI衬底上制造的SOI集成电路，以及制造两者的方法。 SOI衬底包括支撑衬底，沉积在支撑衬底上的蚀刻停止层，依次层叠在蚀刻停止层上的掩埋氧化物层和半导体层。 蚀刻停止层优选地相对于掩埋氧化物层具有蚀刻选择性。 优选形成器件隔离层以限定有源区。 选择性地去除器件隔离，掩埋氧化物和蚀刻停止层，以形成暴露支撑衬底的第一和第二孔而不损坏支撑衬底。 因此，在暴露的支撑衬底上生长的半导体外延层具有没有结晶缺陷的单晶结构。 因此，当在外延层的表面形成杂质区时，可以形成具有优异的漏电流特性的高性能PN二极管。

公开(公告)号：US06667525B2

公开(公告)日：2003-12-23

申请号：US10086565

申请日：2002-03-04

Applicant: Hwa Sung Rhee ,  Nae In Lee ,  Jung Il Lee ,  Sang Su Kim ,  Bae Geum Jong

Inventor： Hwa Sung Rhee ,  Nae In Lee ,  Jung Il Lee ,  Sang Su Kim ,  Bae Geum Jong

IPC: H01L2976

CPC classification number: H01L21/2807 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0262 ,  H01L29/6659

Abstract: A semiconductor device includes a hetero grain stack gate (HGSG). The device includes a semiconductor substrate having a surface, a gate insulating layer formed over the surface of the semiconductor substrate, and a gate electrode formed over the gate insulating layer, wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, and an upper poly-Si layer having a random crystalline structure. In one embodiment, the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure. A method of manufacturing a semiconductor device having an HGSG comprises depositing a gate insulating layer over a surface of a semiconductor substrate, depositing a lower poly-SiGe layer having a columnar crystalline structure over the gate insulating layer, depositing an amorphous Si layer over the lower poly-SiGe layer, and crystallizing the amorphous Si layer to obtain an upper poly-Si layer having a random crystalline structure.

Abstract translation: 半导体器件包括杂质堆叠栅极（HGSG）。 该器件包括具有表面的半导体衬底，形成在半导体衬底的表面上的栅极绝缘层和形成在栅极绝缘层上的栅电极，其中栅极包括具有柱状晶体结构的下部多晶硅层 ，以及具有无规晶体结构的上部多晶硅层。 在一个实施例中，栅电极包括具有柱状晶体结构的下多晶SiGe层，具有无规晶体结构的中间层和具有柱状晶体结构的上多晶硅层。 制造具有HGSG的半导体器件的方法包括在半导体衬底的表面上沉积栅极绝缘层，在栅极绝缘层上沉积具有柱状晶体结构的下部多晶硅层，在下部 多晶SiGe层，并且使非晶Si层结晶，得到具有无规晶体结构的上多晶硅层。