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419 条记录 (耗时 0.071 秒)

    SUBSTRATE RELEASE METHODS AND APPARATUSES
    51.
    发明申请
    SUBSTRATE RELEASE METHODS AND APPARATUSES 有权
    基板释放方法和装置

    公开(公告)号：US20100022074A1

    公开(公告)日：2010-01-28

    申请号：US12473811

    申请日：2009-05-28

    申请人： David Xuan-Qi Wang ,  Mehrdad M. Moslehi

    发明人： David Xuan-Qi Wang ,  Mehrdad M. Moslehi

    IPC分类号： H01L21/762 ,  H01L21/20

    CPC分类号： H01L31/18 ,  H01L21/76259

    摘要： The present disclosure relates to methods and apparatuses for fracturing or breaking a buried porous semiconductor layer to separate a 3-D thin-film semiconductor semiconductor (TFSS) substrate from a 3-D crystalline semiconductor template. The method involves forming a sacrificial porous semiconductor layer on the 3-D features of the template. A variety of techniques may be used to fracture and release the mechanically weak porous semiconductor layer without damaging the TFSS substrate layer or the template layer such as pressure variations, thermal stress generation, and mechanical bending. The methods also allow for processing three dimensional features not possible with current separation processes. Optional cleaning and final lift-off steps may be performed as part of the release step or after the release step.

    摘要翻译： 本公开内容涉及用于将埋入的多孔半导体层断裂或断裂以从3-D晶体半导体模板分离3-D薄膜半导体（TFSS）衬底的方法和装置。 该方法包括在模板的3-D特征上形成牺牲多孔半导体层。 可以使用各种技术来破坏和释放机械上的弱多孔半导体层，而不会损坏TFSS衬底层或模板层，例如压力变化，热应力产生和机械弯曲。 这些方法还允许处理当前分离过程不可能的三维特征。 可以在释放步骤的一部分或释放步骤之后执行可选的清洁和最终剥离步骤。

    SYSTEM ENABLING TRANSACTIONAL MEMORY AND PREDICTION-BASED TRANSACTION EXECUTION METHOD
    53.
    发明申请
    SYSTEM ENABLING TRANSACTIONAL MEMORY AND PREDICTION-BASED TRANSACTION EXECUTION METHOD 有权
    系统启用交易记忆和基于预测的交易执行方法

    公开(公告)号：US20090292884A1

    公开(公告)日：2009-11-26

    申请号：US12463113

    申请日：2009-05-08

    申请人： Hua Yong Wang ,  Charles Brian Hall ,  Yan Qi Wang ,  Zhi Yong Liang ,  Xiao Wei Shen

    发明人： Hua Yong Wang ,  Charles Brian Hall ,  Yan Qi Wang ,  Zhi Yong Liang ,  Xiao Wei Shen

    IPC分类号： G06F12/00 ,  G06N5/02

    CPC分类号： G06F9/528 ,  G06F9/30087 ,  G06F9/30189 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/467 ,  G06F2209/507

    摘要： This invention provides a system enabling Transactional Memory with overflow prediction mechanism, comprising: prediction unit for predicting the mode for the next execution of a transaction based on the final status of the previous execution of the transaction; execution unit for executing the transaction in the execution mode predicted by the prediction unit, wherein the execution mode comprises overflow mode and non-overflow made. According to this invention, before a transaction is executed, it is predicted whether or not the transaction will overflow, and therefore, the execution of the transaction which is necessary to determine whether or not an overflow will occur is saved and the system performance can be improved.

    摘要翻译： 本发明提供一种能够实现具有溢出预测机制的事务性存储器的系统，包括：预测单元，用于基于事务的先前执行的最终状态来预测下一次执行事务的模式; 执行单元，用于在由预测单元预测的执行模式中执行交易，其中执行模式包括溢出模式和非溢出。 根据本发明，在交易执行之前，预测交易是否会溢出，因此，确定是否发生溢出所必需的交易的执行被保存，并且系统性能可以是 改进。

    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM
    54.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE AND SYSTEM 有权
    可变电阻存储器件和系统

    公开(公告)号：US20090251954A1

    公开(公告)日：2009-10-08

    申请号：US12417679

    申请日：2009-04-03

    申请人： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    发明人： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

    IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C11/416

    CPC分类号： G11C16/08 ,  G11C8/12

    摘要： Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

    摘要翻译： 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

    Semiconductor device having memory array, method of writing, and systems associated therewith
    56.
    发明申请
    Semiconductor device having memory array, method of writing, and systems associated therewith 有权
    具有存储器阵列，写入方法和与其相关联的系统的半导体器件

    公开(公告)号：US20090141567A1

    公开(公告)日：2009-06-04

    申请号：US12289937

    申请日：2008-11-07

    申请人： Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

    发明人： Kwang Jin Lee ,  Qi Wang ,  Beak Hyung Cho

    IPC分类号： G11C7/00 ,  G11C7/22

    CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2213/72

    摘要： In one embodiment, the semiconductor device, includes a non-volatile memory cell array, and a control unit configured to generate a mode signal indicating if a flash mode has been enabled. A write circuit is configured to write in the non-volatile memory cell array based on the mode signal such that the write circuit disables erasing the non-volatile memory cell array if the flash mode has not been enabled and instructions to erase one or more cells of the non-volatile memory cell array is received.

    摘要翻译： 在一个实施例中，半导体器件包括非易失性存储单元阵列，以及控制单元，被配置为产生指示闪光模式是否被使能的模式信号。 写电路被配置为基于模式信号写入非易失性存储单元阵列，使得如果闪存模式尚未被使能，则写电路禁止擦除非易失性存储单元阵列，并且指令擦除一个或多个单元 接收非易失性存储单元阵列。

    Power trench MOSFETs having SiGe/Si channel structure
    59.
    发明授权
    Power trench MOSFETs having SiGe/Si channel structure 有权
    具有SiGe / Si沟道结构的功率沟槽MOSFET

    公开(公告)号：US07504691B2

    公开(公告)日：2009-03-17

    申请号：US11469456

    申请日：2006-08-31

    申请人： Chanho Park ,  Qi Wang

    发明人： Chanho Park ,  Qi Wang

    IPC分类号： H01L31/00

    CPC分类号： H01L29/7813 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/49 ,  H01L29/4933 ,  H01L29/66734 ,  H01L29/7782 ,  Y02P70/605

    摘要： Devices, methods, and processes that improve immunity to transient voltages and reduce parasitic impedances. Immunity to unclamped inductive switching events is improved. For example, a trench-gated power MOSFET device having a SiGe source is provided, where the SiGe source reduces parasitic npn transistor gain by reducing hole current in the body or well region, thereby decreasing the likelihood of a latch-up condition. A trench-gated power MOSFET device having a SiGe body or well region is also provided. A SiGe body reduces hole current when the body diode is turned on, thereby reducing reverse recovery power losses. Other device characteristics are also improved. For example, parasitic gate impedance can reduced through the use of a poly SiGe gate. Also, channel resistance can be reduced through the use of a SiGe layer near the device's gate and a thick oxide region can be formed under the trench gate to reduce gate-to-drain capacitance.

    摘要翻译： 提高对瞬态电压的抗扰度并减少寄生阻抗的器件，方法和过程。 提高对松开感应开关事件的抗扰度。 例如，提供了具有SiGe源的沟槽门控功率MOSFET器件，其中SiGe源通过减少主体或阱区中的空穴电流来降低寄生npn晶体管增益，从而降低闩锁状态的可能性。 还提供了具有SiGe体或阱区的沟槽栅功率MOSFET器件。 当体二极管导通时，SiGe体减小空穴电流，从而降低反向恢复功率损耗。 其他装置特性也得到改善。 例如，通过使用多晶SiGe栅极可以减小寄生栅极阻抗。 此外，可以通过在器件栅极附近使用SiGe层来减小沟道电阻，并且可以在沟槽栅极下形成厚的氧化物区域以减小栅极 - 漏极电容。

    NOVEL 7S-ALPHA REGULATORY ELEMENTS FOR EXPRESSING TRANSGENES IN PLANTS
    60.
    发明申请
    NOVEL 7S-ALPHA REGULATORY ELEMENTS FOR EXPRESSING TRANSGENES IN PLANTS 审中-公开
    用于在植物中表达转基因的新型7S-ALPHA法规元素

    公开(公告)号：US20090064378A1

    公开(公告)日：2009-03-05

    申请号：US12197137

    申请日：2008-08-22

    申请人： Qi Wang ,  Patrice DuBois

    发明人： Qi Wang ,  Patrice DuBois

    IPC分类号： A01H5/00 ,  C07H21/00 ,  C11B1/10 ,  C07K14/415 ,  C12N5/04

    CPC分类号： C12N15/8234

    摘要： The present invention provides novel non-coding gene regulatory element polynucleotide molecules isolated or identified from the beta-conglycinin gene of Glycine max and useful for expressing transgenes in plants. The invention further discloses compositions, polynucleotide constructs, transformed host cells, transgenic plants and seeds comprising the regulatory polynucleotide molecules, and methods for preparing and using the same.

    摘要翻译： 本发明提供从大豆的β-伴大豆球蛋白基因中分离或鉴定并用于在植物中表达转基因的新型非编码基因调控元件多核苷酸分子。 本发明还公开了组合物，多核苷酸构建体，转化的宿主细胞，转基因植物和包含调节性多聚核苷酸分子的种子，以及制备和使用其的方法。