公开(公告)号：US20090061608A1

公开(公告)日：2009-03-05

申请号：US11846633

申请日：2007-08-29

Applicant: Tushar P. Merchant ,  Lakshmanna Vishnubhotla ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sriram Kalpat

Inventor： Tushar P. Merchant ,  Lakshmanna Vishnubhotla ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Sriram Kalpat

IPC: H01L21/28

CPC classification number: H01L29/792 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/42332 ,  H01L29/66825

Abstract: A method of depositing a silicon dioxide layer for a semiconductor device. The method includes depositing the silicon dioxide layer to have a silicon concentration of greater than 30 atomic percent and a nitrogen concentration of less than 5 atomic percent. The depositing includes flowing nitric oxide gas with a silicon precursor over a substrate. In one example, the silicon precursor and nitric oxide are flowed over a substrate with the substrate being at a temperature in a range of approximately 600 to approximately 900 degrees Celsius. In one example, the silicon dioxide layer is formed on a layer including charge storage memory material.

Abstract translation: 一种沉积半导体器件的二氧化硅层的方法。 该方法包括沉积二氧化硅层以具有大于30原子百分比的硅浓度和小于5原子％的氮浓度。 沉积包括在衬底上流动具有硅前体的一氧化氮气体。 在一个实例中，硅前体和一氧化氮在衬底上流动，衬底的温度在约600至约900摄氏度的范围内。 在一个示例中，二氧化硅层形成在包括电荷存储存储材料的层上。

公开(公告)号：US20080121967A1

公开(公告)日：2008-05-29

申请号：US11530054

申请日：2006-09-08

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

IPC: H01L29/78 ,  H01L21/3205

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L29/40114 ,  H01L29/513 ,  H01L29/7881

Abstract: A method of forming a semiconductor device, which is preferably a memory cell, includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, wherein each of the plurality of discrete storage elements has a diameter value that is approximately equal to each other, and forming a second dielectric layer over the plurality of discrete storage elements, wherein the second dielectric layer has a thickness, wherein the ratio of the thickness of the second dielectric to the diameter value is less than approximately 0.8. The spacing between the plurality of discrete storage elements may be greater than or equal to approximately the thickness of the second dielectric layer.

Abstract translation: 形成半导体器件的方法，其优选地是存储单元，包括在半导体衬底上形成第一介电层，在第一介电层上形成多个离散存储元件，其中多个离散存储元件中的每一个具有 并且在所述多个分立存储元件上形成第二电介质层，其中所述第二电介质层具有厚度，其中所述第二电介质的厚度与所述直径值的比值小于 约0.8。 多个离散存储元件之间的间隔可以大于或等于第二电介质层的厚度。

公开(公告)号：US07361567B2

公开(公告)日：2008-04-22

申请号：US11043826

申请日：2005-01-26

Applicant: Rajesh A. Rao ,  Ramachandran Muralidhar ,  Bruce E. White

Inventor： Rajesh A. Rao ,  Ramachandran Muralidhar ,  Bruce E. White

IPC: H01L21/331 ,  H01L21/20 ,  H01L21/8242 ,  H01L21/31 ,  H01L21/469

CPC classification number: H01L29/42348 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/42332 ,  H01L29/513 ,  H01L29/518

Abstract: A nanocrystal non-volatile memory (NVM) has a dielectric between the control gate and the nanocrystals that has a nitrogen content sufficient to reduce the locations in the dielectric where electrons can be trapped. This is achieved by grading the nitrogen concentration. The concentration of nitrogen is highest near the nanocrystals where the concentration of electron/hole traps tend to be the highest and is reduced toward the control gate where the concentration of electron/hole traps is lower. This has been found to have the beneficial effect of reducing the number of locations where charge can be trapped.

Abstract translation: 纳米晶体非易失性存储器（NVM）在控制栅极和纳米晶体之间具有电介质，其具有足够的氮含量以减少电介质中的电子被俘获的位置。 这是通过对氮浓度进行分级而实现的。 靠近纳米晶体的氮浓度最高，其中电子/空穴阱的浓度趋于最高，并且朝向电子/空穴陷阱的浓度较低的对照栅极减小。 已经发现这具有减少电荷被捕获的位置数量的有益效果。

公开(公告)号：US20080026526A1

公开(公告)日：2008-01-31

申请号：US11459837

申请日：2006-07-25

Applicant: Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

Inventor： Rajesh A. Rao ,  Tien Ying Luo ,  Ramachandran Muralidhar ,  Robert F. Steimle ,  Sherry G. Straub

IPC: H01L21/336 ,  H01L21/3205

CPC classification number: H01L21/28273 ,  H01L21/28282 ,  H01L21/32134 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11573 ,  Y10S977/774 ,  Y10S977/779 ,  Y10S977/78 ,  Y10S977/943

Abstract: A method of making a semiconductor device includes a substrate having a semiconductor layer having a first portion for non-volatile memory and a second portion exclusive of the first portion. A first dielectric layer is formed on the semiconductor layer. A plasma nitridation is performed on the first dielectric layer. A first plurality of nanoclusters is formed over the first portion and a second plurality of nanoclusters over the second portion. The second plurality of nanoclusters is removed. A second dielectric layer is formed over the semiconductor layer. A conductive layer is formed over the second dielectric layer.

Abstract translation: 制造半导体器件的方法包括具有半导体层的衬底，该半导体层具有用于非易失性存储器的第一部分和不包括第一部分的第二部分。 在半导体层上形成第一电介质层。 在第一电介质层上进行等离子体氮化。 在第一部分上形成第一多个纳米团簇，并在第二部分上形成第二多个纳米团簇。 第二组纳米团簇被去除。 在半导体层上方形成第二电介质层。 在第二电介质层上形成导电层。

公开(公告)号：US07160775B2

公开(公告)日：2007-01-09

申请号：US10912825

申请日：2004-08-06

Applicant: Erwin J. Prinz ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Robert F. Steimle ,  Craig T. Swift ,  Bruce E. White

Inventor： Erwin J. Prinz ,  Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Robert F. Steimle ,  Craig T. Swift ,  Bruce E. White

IPC: H01L21/336

CPC classification number: B82Y10/00 ,  G11C16/0475 ,  G11C16/14 ,  G11C2216/06 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42332

Abstract: In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.

Abstract translation: 在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电 场到纳米团簇放电半导体器件。 施加紫外线（UV）光时可能会发生电场。 在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。

公开(公告)号：US06969883B2

公开(公告)日：2005-11-29

申请号：US10950855

申请日：2004-09-27

Applicant: Gowrishankar L. Chindalore ,  Rajesh A. Rao ,  Jane A. Yater

Inventor： Gowrishankar L. Chindalore ,  Rajesh A. Rao ,  Jane A. Yater

IPC: G11C5/00 ,  G11C16/28 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/76

CPC classification number: H01L27/11568 ,  B82Y10/00 ,  G11C16/28 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/105 ,  H01L27/11573

Abstract: A non-volatile memory (30) comprises nanocrystal memory cells (50, 51, 53). The program and erase threshold voltage of the memory cell transistors (50, 51, 53) increase as a function of the number of program/erase operations. During a read operation, a reference transistor (46) provides a reference current for comparing with a cell current. The reference transistor (46) is made from a process similar to that used to make the memory cell transistors (50, 51, 53), except that the reference transistor (46) does not include nanocrystals. By using a similar process to make both the reference transistor (46) and the memory cell transistors (50, 51, 53), a threshold voltage of the reference transistor (46) will track the threshold voltage shift of the memory cell transistor (50, 51, 53). A read control circuit (42) is provided to bias the gate of the reference transistor (46). The read control circuit (42) senses a drain current of the reference transistor (46) and adjusts the gate bias voltage to maintain the reference current at a substantially constant value relative to the cell current.

Abstract translation: 非易失性存储器（30）包括纳米晶体存储单元（50,51,53）。 存储单元晶体管（50,51,53）的编程和擦除阈值电压作为编程/擦除操作的次数增加。 在读取操作期间，参考晶体管（46）提供用于与单元电流进行比较的参考电流。 除了参考晶体管（46）不包括纳米晶体之外，参考晶体管（46）由与制造存储单元晶体管（50,51,53）类似的工艺制成。 通过使用类似的工艺来使参考晶体管（46）和存储单元晶体管（50,51,53）同时工作，参考晶体管（46）的阈值电压将跟踪存储单元晶体管（50）的阈值电压偏移 ，51,53）。 提供读控制电路（42）以偏置参考晶体管（46）的栅极。 读取控制电路（42）感测参考晶体管（46）的漏极电流并调整栅极偏置电压，以使参考电流相对于单元电流保持在基本恒定的值。

公开(公告)号：US06784103B1

公开(公告)日：2004-08-31

申请号：US10442500

申请日：2003-05-21

Applicant: Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar

Inventor： Rajesh A. Rao ,  Tushar P. Merchant ,  Ramachandran Muralidhar

IPC: H01L2144

CPC classification number: B82Y10/00 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28273 ,  H01L29/42332

Abstract: Nanocrystals (22) are formed in a semiconductor, such as for example, in a memory having a floating gate. A dielectric (18) overlies a substrate (12) and is placed in a chemical vapor deposition chamber (34). A first precursor gas, such as disilane (36), is flowed into the chemical vapor deposition chamber during a first phase to nucleate the nanocrystals (22) on the dielectric with first predetermined processing conditions existing within the chemical vapor deposition chamber for a first time period. A second precursor gas, such as silane, is flowed into the chemical vapor deposition chamber during a second phase subsequent to the first phase to grow the nanocrystals under second predetermined processing conditions existing within the chemical vapor deposition chamber for a second time period.

Abstract translation: 纳米晶体（22）形成在半导体中，例如在具有浮动栅极的存储器中。 电介质（18）覆盖在衬底（12）上并且被放置在化学气相沉积室（34）中。 第一前体气体，例如乙硅烷（36）在第一阶段期间流入化学气相沉积室，以使化学气相沉积室内存在的第一预定处理条件第一次使介质上的纳米晶体（22）成核 期。 第二前体气体，例如硅烷，在第一阶段之后的第二阶段期间流入化学气相沉积室，以在第二时间段内在化学气相沉积室内存在的第二预定处理条件下生长纳米晶体。