公开(公告)号：US08710560B2

公开(公告)日：2014-04-29

申请号：US11835814

申请日：2007-08-08

申请人： Yuan-Chih Hsieh ,  Shih-Chang Liu ,  Shih-Chi Fu ,  Tzu-Hsuan Hsu ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

发明人： Yuan-Chih Hsieh ,  Shih-Chang Liu ,  Shih-Chi Fu ,  Tzu-Hsuan Hsu ,  Chung-Yi Yu ,  Gwo-Yuh Shiau ,  Chia-Shiung Tsai

IPC分类号： H01L31/062

CPC分类号： H01L27/14643 ,  H01L24/05 ,  H01L27/14636 ,  H01L2224/05556 ,  H01L2924/12043 ,  H01L2924/00

摘要： A semiconductor device includes a semiconductor substrate having a front surface and a back surface, elements formed on the substrate, interconnect metal layers formed over the front surface of the substrate, including a topmost interconnect metal layer, an inter-metal dielectric for insulating each of the plurality of interconnect metal layers, and a bonding pad disposed within the inter-metal dielectric, the bonding pad in contact with one of the interconnect metal layers other than the topmost interconnect metal layer.

摘要翻译： 半导体器件包括具有前表面和后表面的半导体衬底，形成在衬底上的元件，形成在衬底的前表面上的互连金属层，包括最上面的互连金属层，用于绝缘的金属间电介质 所述多个互连金属层和设置在所述金属间电介质内的接合焊盘，所述接合焊盘与所述互连金属层中的一个互连金属层之外的最上面的互连金属层接触。

公开(公告)号：US08610229B2

公开(公告)日：2013-12-17

申请号：US13087192

申请日：2011-04-14

申请人： Hung-Wen Hsu ,  Shih-Chang Liu ,  Yeur-Luen Tu

发明人： Hung-Wen Hsu ,  Shih-Chang Liu ,  Yeur-Luen Tu

IPC分类号： H01L27/146

CPC分类号： H01L27/14685 ,  H01L27/14623 ,  H01L27/14627 ,  H01L27/1464

摘要： The present disclosure provides an image sensor device and a method for manufacturing the image sensor device. An exemplary image sensor device includes a substrate having a front surface and a back surface; a plurality of sensor elements disposed at the front surface of the substrate, each of the plurality of sensor elements being operable to sense radiation projected towards the back surface of the substrate; a radiation-shielding feature disposed over the back surface of the substrate and horizontally disposed between each of the plurality of sensor elements; a dielectric feature disposed between the back surface of the substrate and the radiation-shielding feature; and a metal layer disposed along sidewalls of the dielectric feature.

摘要翻译： 本公开提供了一种图像传感器装置和用于制造图像传感器装置的方法。 示例性的图像传感器装置包括具有前表面和后表面的基板; 设置在所述基板的前表面处的多个传感器元件，所述多个传感器元件中的每一个可操作以感测朝向所述基板的后表面投射的辐射; 辐射屏蔽特征设置在所述基板的所述背表面上并且水平地设置在所述多个传感器元件中的每一个之间; 设置在基板的背面和辐射屏蔽特征之间的电介质特征; 以及沿着电介质特征的侧壁设置的金属层。

公开(公告)号：US08501572B2

公开(公告)日：2013-08-06

申请号：US12874362

申请日：2010-09-02

申请人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Chun-Tsung Kuo ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L21/331

CPC分类号： H01L29/66242 ,  H01L29/0821 ,  H01L29/66287 ,  H01L29/66318 ,  H01L29/732 ,  H01L29/7371 ,  H01L29/7378

摘要： The present disclosure provides a bipolar junction transistor (BJT) device and methods for manufacturing the BJT device. In an embodiment, the BJT device includes: a semiconductor substrate having a collector region, and a material layer disposed over the semiconductor layer. The material layer has a trench therein that exposes a portion of the collector region. A base structure, spacers, and emitter structure are disposed within the trench of the material layer. Each spacer has a top width and a bottom width, the top width being substantially equal to the bottom width.

摘要翻译： 本公开提供了一种双极结型晶体管（BJT）器件和用于制造BJT器件的方法。 在一个实施例中，BJT器件包括：具有集电极区域和设置在半导体层上的材料层的半导体衬底。 材料层在其中具有暴露出集电极区域的一部分的沟槽。 基底结构，间隔物和发射体结构设置在材料层的沟槽内。 每个间隔物具有顶部宽度和底部宽度，顶部宽度基本上等于底部宽度。

公开(公告)号：US08278122B2

公开(公告)日：2012-10-02

申请号：US12696771

申请日：2010-01-29

申请人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Jiech-Fun Lu ,  Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L21/00

CPC分类号： H01L43/12 ,  H01L27/222

摘要： A method of forming an integrated circuit structure includes forming a bottom electrode layer over a substrate; forming magnetic tunnel junction (MTJ) layers over the bottom electrode layer; patterning the MTJ layers to form a MTJ stack; forming a dielectric layer covering the MTJ stack; forming an opening in the dielectric layer to expose a portion of the MTJ stack; filling the opening with a top electrode material; and performing a planarization to the top electrode material. After the step of performing the planarization, the top electrode material and the dielectric layer are patterned, wherein a first portion of the top electrode material in the opening forms a top electrode, and a second portion of the top electrode material forms a metal strip over the dielectric layer and connected to the top electrode.

摘要翻译： 形成集成电路结构的方法包括在衬底上形成底电极层; 在底部电极层上形成磁隧道结（MTJ）层; 图案化MTJ层以形成MTJ堆叠; 形成覆盖所述MTJ叠层的电介质层; 在所述电介质层中形成开口以暴露所述MTJ堆叠的一部分; 用顶部电极材料填充开口; 并对顶部电极材料进行平面化。 在执行平面化的步骤之后，对顶部电极材料和电介质层进行图案化，其中开口中的顶部电极材料的第一部分形成顶部电极，并且顶部电极材料的第二部分形成金属带 电介质层并连接到顶部电极。

公开(公告)号：US20110248328A1

公开(公告)日：2011-10-13

申请号：US12757172

申请日：2010-04-09

申请人： Ming-Huei Shen ,  Tsun Kai Tsao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Ming-Huei Shen ,  Tsun Kai Tsao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/7881

摘要： A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.

摘要翻译： 提供半导体结构。 半导体结构包括半导体衬底上的第一浮置栅极，浮置栅极具有凹面侧面; 第一个浮动门上的第一个控制门; 与所述第一控制栅极相邻的第一间隔件; 与所述第一浮动栅极的第一侧相邻的第一字线，具有第一距离; 以及与所述第一浮动栅极的第二侧相邻的擦除栅极，其具有小于所述第一距离的第二距离，所述第二侧与所述第一侧相对。

公开(公告)号：US07785966B2

公开(公告)日：2010-08-31

申请号：US11614677

申请日：2006-12-21

申请人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Wen-Ting Chu ,  Chi-Hsin Lo ,  Chia-Shiung Tsai

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  Y10S438/981

摘要： An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.

摘要翻译： 一种用于制造具有减小且更均匀的前向隧道电压的闪存单元的浮动栅极结构的改进方法。 该方法可以包括以下步骤：在衬底上形成至少两个浮动栅极; 在每个浮动栅极上形成掩模，每个掩模具有与给定厚度的相应一个浮动栅极的尖端相邻的部分，其中掩模部分的给定厚度彼此不同; 并且蚀刻掩模以将掩模部分的不同给定厚度减小到减小的厚度，其中掩模的厚度减小部分具有均匀的厚度。

公开(公告)号：US07700473B2

公开(公告)日：2010-04-20

申请号：US11784633

申请日：2007-04-09

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧上的尺寸上横向减小以产生底切。

公开(公告)号：US07687794B2

公开(公告)日：2010-03-30

申请号：US11781728

申请日：2007-07-23

申请人： Shih-Chang Liu ,  Chia-Shiung Tsai

发明人： Shih-Chang Liu ,  Chia-Shiung Tsai

IPC分类号： H01L29/02

CPC分类号： H01L45/16 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

摘要： A PCM (phase change memory) cell in a PCRAM (phase change random access memory) semiconductor device includes a phase change material subjacently contacted by a heater film. The phase change material is formed over a surface that is a generally planar surface with at least a downwardly extending recess. The phase change material fills the recess and contacts the upper edge of the heater film that forms the bottom of the recess. After a planar surface is initially formed, a selective etching process is used to recede the top edge of the heater film below the planar surface using a selective and isotropic etching process.

摘要翻译： PCRAM（相变随机存取存储器）半导体器件中的PCM（相变存储器）单元包括由加热膜隐藏接触的相变材料。 相变材料形成在具有至少一个向下延伸的凹部的大致平坦的表面的表面上。 相变材料填充凹部并接触形成凹部底部的加热器膜的上边缘。 在初始形成平坦表面之后，使用选择性蚀刻工艺来使用选择性和各向同性蚀刻工艺将加热器膜的顶部边缘退回到平坦表面下方。

公开(公告)号：US20080248620A1

公开(公告)日：2008-10-09

申请号：US11784633

申请日：2007-04-09

申请人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

发明人： Shih-Chang Liu ,  Ming-Hui Shen ,  Chi-Hsin Lo ,  Chia-Shiung Tsai ,  Yi-Shin Chu

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/6656 ,  Y10S438/945

摘要： A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

摘要翻译： 一种用于制造门控半导体器件的方法，以及由执行该方法产生的器件。 在一个优选实施例中，该方法包括形成用于在基板上形成的交替绝缘和导电材料的一层或多层上形成栅极的硬掩模。 硬掩模优选包括三层; 下氮化物层，中间氧化物和上氮化物层。 在该实施例中，中间氧化物层与硬掩模的其余部分形成，然后以侧向尺寸减小，优选使用DHF浸渍。 形成在栅极结构上方的电介质层，包括硬掩模，然后被回蚀，自对准成为尺寸减小的氧化物层。 此外，当存在两个导电（即栅极层）时，下层在至少一侧的横向尺寸上横向减小以产生底切。

公开(公告)号：US20080121975A1

公开(公告)日：2008-05-29

申请号：US11592290

申请日：2006-11-03

申请人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

发明人： Chang-Jen Hsieh ,  Hung-Cheng Sung ,  Wen-Ting Chu ,  Chen-Ming Huang ,  Ya-Chen Kao ,  Shih-Chang Liu ,  Chi-Hsin Lo ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521

摘要： Split-gate memory cells and fabrication methods thereof. A split-gate memory cell comprises a plurality of isolation regions formed on a semiconductor substrate along a first direction, between two adjacent isolation regions defining an active region having a pair of drains and a source region. A pair of floating gates are disposed on the active regions and self-aligned with the isolation regions, wherein a top level of the floating gate is equal to a top level of the isolation regions. A pair of control gates are self-aligned with the floating gates and disposed on the floating gates along a second direction. A source line is disposed between the pair of control gates along the second direction. A pair of select gates are disposed on the outer sidewalls of the pair of control gates along the second direction.

摘要翻译： 分离栅存储单元及其制造方法。 分离栅极存储单元包括沿着第一方向形成在半导体衬底上的多个隔离区域，在限定具有一对漏极和源极区域的有源区域的两个相邻隔离区域之间。 一对浮置栅极设置在有源区上并与隔离区自对准，其中浮置栅极的顶层等于隔离区的顶层。 一对控制栅极与浮动栅极自对准并沿着第二方向设置在浮动栅极上。 源极线沿第二方向设置在该对控制栅极之间。 一对选择栅极沿着第二方向设置在该对控制栅极的外侧壁上。