公开(公告)号：US20070001212A1

公开(公告)日：2007-01-04

申请号：US11431273

申请日：2006-05-10

Applicant: Woon-Kyung Lee ,  Jeong-Hyuk Choi

Inventor： Woon-Kyung Lee ,  Jeong-Hyuk Choi

IPC: H01L29/788 ,  H01L21/8238

CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

Abstract: A NAND-type memory device may include first and second selection transistors on a semiconductor substrate and a plurality of memory cell transistors coupled in series between the first and second selection transistors. A first source/drain region may be shared between the first selection transistor and a first of the memory cell transistors, and a second source/drain region may be shared between the second selection transistor and a last of the memory cell transistors. Moreover, a portion of at least one of the first and/or second source/drain regions may be recessed relative to a surface of the semiconductor substrate. Related methods are also discussed.

Abstract translation: NAND型存储器件可以包括半导体衬底上的第一和第二选择晶体管和串联耦合在第一和第二选择晶体管之间的多个存储单元晶体管。 第一源/漏区可以在第一选择晶体管和第一存储单元晶体管之间共享，并且第二源/漏区可以在第二选择晶体管和最后的存储单元晶体管之间共享。 此外，第一和/或第二源极/漏极区域中的至少一个的一部分可以相对于半导体衬底的表面凹陷。 还讨论了相关方法。

公开(公告)号：US20060231885A1

公开(公告)日：2006-10-19

申请号：US11455888

申请日：2006-06-20

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L29/76 ,  H01L29/00

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11534 ,  H01L27/11568

Abstract: The present invention provides a semiconductor device in which the gate is self-aligned to the device isolation film and a fabricating method thereof. A device isolation film restricting an active region is disposed on a portion of a semiconductor substrate, and a word line is across over the device isolation film. A gate pattern is disposed between the word line and the active region, and a tunnel oxide film is disposed between the gate pattern and the active region. The gate pattern comprises a floating gate pattern, a gate interlayer dielectric film pattern and a control gate electrode pattern deposited in the respective order, and has a sidewall self-aligned to the device isolation film. To form the gate pattern having the sidewall self-aligned to the device isolation film, a gate insulation film and a gate material film are formed in the respective order on the semiconductor substrate.

公开(公告)号：US07008848B2

公开(公告)日：2006-03-07

申请号：US10713117

申请日：2003-11-17

Applicant: Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

Inventor： Woon-kyung Lee ,  He-jueng Lee ,  Eui-do Kim

IPC: H01L21/8236

CPC classification number: H01L27/112 ,  H01L27/1126

Abstract: A mask read only memory (ROM) and a method of fabricating the same is provided. This mask ROM and related method is capable of reducing the pitch of buried impurity diffusion regions. In the mask ROM fabrication process, a gate insulation layer is formed over a semiconductor substrate, and parallel conductive layer patterns are formed on the gate insulation layer. These conductive layer patterns are separated from each other by a first predetermined interval and extend in the same direction. Ion implantation is then carried out using the conductive layer patterns as a mask to form buried impurity diffusion regions near the semiconductor substrate between the conductive layer patterns. A conductive layer for use in forming word lines is then formed over the entire surface of the resultant structure, and both the conductive layer and the conductive layer patterns are etched so as to form word lines and pad conductive layers. The word lines are formed to be parallel to each other, are separated from each other by a second predetermined interval, and extend in a direction perpendicular to the buried impurity diffusion regions. The pad conductive layers, which form ohmic contacts with the word lines, are formed in an island shape channel regions. These channel regions are defined as the areas between the buried impurity diffusion regions that are overlapped by the word lines.

Abstract translation: 提供了一种掩模只读存储器（ROM）及其制造方法。 该掩模ROM和相关方法能够减少掩埋的杂质扩散区的间距。 在掩模ROM制造工艺中，在半导体衬底上形成栅极绝缘层，并且在栅极绝缘层上形成平行的导电层图案。 这些导电层图案彼此分开第一预定间隔并沿相同的方向延伸。 然后使用导电层图案作为掩模进行离子注入，以在导电层图案之间的半导体衬底附近形成掩埋的杂质扩散区。 然后在所得结构的整个表面上形成用于形成字线的导电层，并且蚀刻导电层和导电层图案，以形成字线和焊盘导电层。 字线形成为彼此平行，彼此分开第二预定间隔，并且在垂直于埋置的杂质扩散区域的方向上延伸。 与字线形成欧姆接触的焊盘导电层形成为岛状沟道区域。 这些沟道区域被定义为由字线重叠的掩埋杂质扩散区域之间的区域。

公开(公告)号：US20050118798A1

公开(公告)日：2005-06-02

申请号：US11029832

申请日：2005-01-04

Applicant: Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

Inventor： Sun-Young Kim ,  Woon-Kyung Lee ,  Dong-Whee Kwon

IPC: H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L29/788 ,  H01L21/4763

CPC classification number: H01L21/76897 ,  H01L21/76895

Abstract: A gate-contact structure and a method for forming the same are provided. The structure includes a device isolation layer pattern formed at a semiconductor substrate to define an active region; and a gate electrode and a capping pattern, which are sequentially stacked on the semiconductor substrate across the device isolation layer pattern. The capping pattern includes a first gate contact hole that exposes a top surface of the gate electrode. An interlayer insulation layer pattern including a second gate contact hole is disposed to cover an entire surface of the semiconductor substrate including the gate electrode and the capping pattern. The second gate contact hole penetrates the first gate contact hole to expose the top surface of the gate electrode. A gate contact plug is disposed to be connected to the top surface of the gate electrode through the second gate contact hole. Accordingly, the interlayer insulation layer pattern is intervened between the gate contact plug and a sidewall of the capping pattern.

Abstract translation: 提供了栅极接触结构及其形成方法。 该结构包括形成在半导体衬底上以限定有源区的器件隔离层图案; 以及栅电极和封盖图案，其跨越器件隔离层图案依次堆叠在半导体衬底上。 封盖图案包括暴露栅电极的顶表面的第一栅极接触孔。 设置包括第二栅极接触孔的层间绝缘层图案以覆盖包括栅电极和封盖图案的半导体衬底的整个表面。 第二栅极接触孔穿过第一栅极接触孔以暴露栅电极的顶表面。 栅极接触插头设置成通过第二栅极接触孔连接到栅电极的顶表面。 因此，层间绝缘层图案介于栅极接触插塞和封盖图案的侧壁之间。

公开(公告)号：US06531360B2

公开(公告)日：2003-03-11

申请号：US09948424

申请日：2001-09-07

Applicant: Woon-Kyung Lee

Inventor： Woon-Kyung Lee

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11546

Abstract: A method of manufacturing a flash memory device is characterized by preventing photoresist patterns from being formed directly on or removed directly from a surface of the substrate or the dielectric layer. This is accomplished by separately forming a control gate layer of transistors in a cell area of the substrate and a gate layer of transistors in a peripheral circuit area of the substrate. The method of the present invention includes the steps of forming in a peripheral circuit area of the substrate a gate insulating layer for both high and low voltage regions of the peripheral circuit area and then forming the gate conduction layer on the gate insulating layer. The method of the present invention further comprises the steps of forming in a cell area of the substrate a transistor structure composed of a tunneling gate insulating layer, a floating gate layer, a dielectric layer, and a control gate layer.

公开(公告)号：US06346733B1

公开(公告)日：2002-02-12

申请号：US09345581

申请日：1999-06-30

Applicant: Woon-Kyung Lee ,  Youn-Ho Lee ,  Eui-Do Kim

Inventor： Woon-Kyung Lee ,  Youn-Ho Lee ,  Eui-Do Kim

IPC: H01L2976

CPC classification number: H01L27/1126 ,  G11C17/126 ,  H01L27/112 ,  Y10S438/926

Abstract: A nonvolatile memory device is provided in which cell uniformity is significantly improved. The device includes a plurality of burial N+ diffusion layers extending over the surface of a semiconductor substrate. The plurality of burial N+ diffusion layers are the source/drains of cell transistors and the sub bit-lines of the memory cell array. The device additionally includes a plurality of word lines formed over the semiconductor substrate with gate dielectrics interposed therebetween. The plurality of word lines extend perpendicularly to the burial N+ diffusion layers. A plurality of select lines extend parallel to the word lines and selectively transfer external electrical signals via main bit-lines to the sub bit-lines. The main bit-lines extend parallel to said sub bit-lines. Finally, dummy lines extend parallel to the word lines in the spaces between the select lines and the adjacent word lines.

Abstract translation: 提供了一种非易失性存储器件，其中电池均匀性显着提高。 该装置包括在半导体衬底的表面上延伸的多个埋入N +扩散层。 多个埋置N +扩散层是单元晶体管的源极/漏极和存储单元阵列的子位线。 该器件还包括形成在半导体衬底上的多个字线，其间插入栅极电介质。 多个字线垂直于埋藏的N +扩散层延伸。 多个选择线平行于字线延伸，并且经由主位线选择性地将外部电信号传送到子位线。 主位线平行于所述子位线延伸。 最后，虚拟线平行于选择线和相邻字线之间的空格中的字线延伸。

公开(公告)号：US09209244B2

公开(公告)日：2015-12-08

申请号：US13717803

申请日：2012-12-18

Applicant: Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

Inventor： Jae-Joo Shim ,  Han-Soo Kim ,  Woon-Kyung Lee ,  Ju-Young Lim ,  Sung-Min Hwang

IPC: H01L29/06 ,  H01L27/02 ,  H01L27/115

CPC classification number: H01L29/0657 ,  H01L27/0207 ,  H01L27/1157 ,  H01L27/11582

Abstract: Provided is a semiconductor device that includes first and second isolation patterns disposed on a substrate. Alternately stacked interlayer insulating patterns and a conductive patterns are disposed on a surface of the substrate between the first and second isolation patterns. A support pattern penetrates the conductive patterns and the interlayer insulating patterns and has a smaller width than the first and second isolation patterns. First and second vertical structures are disposed between the first isolation and the support pattern and penetrate the conductive patterns and the interlayer insulating patterns. A second vertical structure is disposed between the second isolation pattern and the support pattern and penetrates the conductive patterns and the interlayer insulating patterns. A distance between top and bottom surfaces of the support pattern is greater than a distance between a bottom surface of the support pattern and the surface of the substrate.

Abstract translation: 提供了包括设置在基板上的第一和第二隔离图案的半导体器件。 交替层叠的层间绝缘图案和导电图案设置在第一和第二隔离图案之间的基板的表面上。 支撑图案穿透导电图案和层间绝缘图案，并且具有比第一和第二隔离图案更小的宽度。 第一和第二垂直结构设置在第一隔离和支撑图案之间并且穿透导电图案和层间绝缘图案。 第二垂直结构设置在第二隔离图案和支撑图案之间并且穿透导电图案和层间绝缘图案。 支撑图案的顶表面和底表面之间的距离大于支撑图案的底表面和基底表面之间的距离。

公开(公告)号：US08609496B2

公开(公告)日：2013-12-17

申请号：US13542777

申请日：2012-07-06

Applicant: Dongyean Oh ,  Woon-kyung Lee

Inventor： Dongyean Oh ,  Woon-kyung Lee

IPC: H01L21/8232

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L21/823493

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。

公开(公告)号：US08264025B2

公开(公告)日：2012-09-11

申请号：US12275369

申请日：2008-11-21

Applicant: Seung-Jun Lee ,  Woon-Kyung Lee

Inventor： Seung-Jun Lee ,  Woon-Kyung Lee

IPC: H01L29/76

CPC classification number: H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

Abstract: A nonvolatile memory device and a method of forming a nonvolatile memory device are provided. The nonvolatile memory device includes an active region of a semiconductor substrate defined by a device isolation layer, a tunnel insulating structure disposed on the active region, and a charge storage structure disposed on the tunnel insulating structure. The nonvolatile memory device also includes a gate interlayer dielectric layer disposed on the charge storage structure, and a control gate electrode disposed on the gate interlayer dielectric layer. The charge storage structure includes an upper charge storage structure and a lower charge storage structure, and the upper charge storage structure has a higher impurity concentration than the lower charge storage structure.

Abstract translation: 提供了非易失性存储器件和形成非易失性存储器件的方法。 非易失性存储器件包括由器件隔离层限定的半导体衬底的有源区，设置在有源区上的隧道绝缘结构，以及设置在隧道绝缘结构上的电荷存储结构。 非易失性存储器件还包括设置在电荷存储结构上的栅极层间介质层和设置在栅极层间介质层上的控制栅电极。 电荷存储结构包括上电荷存储结构和较低电荷存储结构，并且上电荷存储结构具有比下电荷存储结构更高的杂质浓度。

公开(公告)号：US08237230B2

公开(公告)日：2012-08-07

申请号：US12631109

申请日：2009-12-04

Applicant: Dongyean Oh ,  Woon-kyung Lee

Inventor： Dongyean Oh ,  Woon-kyung Lee

IPC: H01L29/76

CPC classification number: H01L27/088 ,  H01L21/823462 ,  H01L21/823493

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device. The semiconductor device can include first transistors that include a first gate insulating layer having a first thickness and second transistors include a second gate insulating layer having a second thickness less than the first thickness. At least one of the transistors formed on the first or second gate insulating layers is directly over a dummy well.

Abstract translation: 提供半导体器件和制造半导体器件的方法。 半导体器件可以包括第一晶体管，其包括具有第一厚度的第一栅极绝缘层，第二晶体管包括具有小于第一厚度的第二厚度的第二栅极绝缘层。 形成在第一或第二栅极绝缘层上的晶体管中的至少一个直接在虚拟阱上。