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    DRAM memory cell
    53.
    发明授权
    DRAM memory cell 失效
    DRAM存储单元

    公开(公告)号：US07368752B2

    公开(公告)日：2008-05-06

    申请号：US10839800

    申请日：2004-05-06

    申请人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    发明人： Richard J. Luyken ,  Franz Hofmann ,  Lothar Risch ,  Dirk Manger ,  Wolfgang Rösner ,  Till Schlösser ,  Michael Specht

    IPC分类号： H01L27/108 ,  H01L29/12 ,  H01L31/112

    CPC分类号： H01L27/10823 ,  H01L27/10808 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10891 ,  H01L29/7851

    摘要： A DRAM memory cell is provided with a selection transistor, which is arranged horizontally at a semiconductor substrate surface and has a first source/drain electrode, a second source/drain electrode, a channel layer arranged between the first and the second source/drain electrode in the semiconductor substrate, and a gate electrode, which is arranged along the channel layer and is electrically insulated from the channel layer, a storage capacitor, which has a first capacitor electrode and a second capacitor electrode, insulated from the first capacitor electrode, one of the capacitor electrodes of the storage capacitor being electrically conductively connected to one of the source/drain electrodes of the selection transistor, and a semiconductor substrate electrode on the rear side, the gate electrode enclosing the channel layer at at least two opposite sides.

    摘要翻译： DRAM存储单元设置有选择晶体管，该晶体管被水平地布置在半导体衬底表面处并且具有第一源极/漏极，第二源极/漏极，布置在第一和第二源极/漏极之间的沟道层 在所述半导体基板中，沿着所述沟道层配置并与所述沟道层电绝缘的栅电极具有与所述第一电容电极绝缘的第一电容电极和第二电容电极的保持电容器， 所述存储电容器的电容器电极与所述选择晶体管的源极/漏极之一导电地连接，并且在后侧具有半导体衬底电极，所述栅电极在至少两个相对的两侧包围所述沟道层。

    Non-volatile memory cells and methods for fabricating non-volatile memory cells
    54.
    发明授权
    Non-volatile memory cells and methods for fabricating non-volatile memory cells 有权
    非易失性存储单元和用于制造非易失性存储单元的方法

    公开(公告)号：US07352018B2

    公开(公告)日：2008-04-01

    申请号：US11187693

    申请日：2005-07-22

    申请人： Michael Specht ,  Franz Hofmann ,  Johannes Luyken

    发明人： Michael Specht ,  Franz Hofmann ,  Johannes Luyken

    IPC分类号： H01L27/10 ,  H01L29/73

    CPC分类号： H01L27/11568 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/785

    摘要： The invention relates to a method for fabricating stacked non-volatile memory cells. Further, the invention relates to stacked non-volatile memory cells. The invention particularly relates to the field of non-volatile NAND memories having non-volatile stacked memory cells. The stacked non-volatile memory cells are formed on a semiconductor wafer, having a bulk semi-conductive substrate and an SOI semi-conductive layer and are arranged as a bulk FinFET transistor and an SOI FinFet transistor being arranged on top of the bulk FinFET transistor. Both the FinFET transistor and the SOI FinFet transistor are attached to a common charge-trapping layer. A word line with sidewalls is arranged on top of said patterned charge-trapping layer and a spacer oxide layer is arranged on the sidewalls of said word line.

    摘要翻译： 本发明涉及一种用于制造堆叠的非易失性存储单元的方法。 此外，本发明涉及堆叠的非易失性存储单元。 本发明特别涉及具有非易失性堆叠存储单元的非易失性NAND存储器的领域。 层叠的非易失性存储单元形成在具有体半导体基板和SOI半导电层的半导体晶片上，并且被布置为体FinFET晶体管，并且SOI FinFet晶体管布置在体FinFET晶体管的顶部 。 FinFET晶体管和SOI FinFet晶体管都连接到公共的电荷俘获层。 具有侧壁的字线被布置在所述图案化的电荷捕获层的顶部上，并且间隔氧化物层被布置在所述字线的侧壁上。

    Memory array having an interconnect and method of manufacture
    55.
    发明申请
    Memory array having an interconnect and method of manufacture 审中-公开
    具有互连和制造方法的存储器阵列

    公开(公告)号：US20080074927A1

    公开(公告)日：2008-03-27

    申请号：US11525547

    申请日：2006-09-22

    申请人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    发明人： Franz Hofmann ,  Michael Specht ,  Nicolas Nagel ,  Josef Willer

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0483 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568

    摘要： A memory array includes first, second, third and forth memory cell strings. Each of the first, second, third, and fourth memory cell strings includes a number of serially-coupled memory cells, including a first memory cell and a last memory cell. A first interconnect is coupled to a first bit line and to each of the first, second, third and fourth memory cell strings. The first interconnect includes first, second, third and fourth string input select gates. Each input select gate has a first terminal coupled to the first bit line, and a second terminal coupled to one of the respective first, second, third or fourth memory cell strings.

    摘要翻译： 存储器阵列包括第一，第二，第三和第四存储器单元串。 第一，第二，第三和第四存储器单元串中的每一个包括多个串行耦合的存储器单元，包括第一存储单元和最后存储单元。 第一互连耦合到第一位线和第一，第二，第三和第四存储器单元串中的每一个。 第一互连包括第一，第二，第三和第四串输入选择门。 每个输入选择栅极具有耦合到第一位线的第一端子和耦合到相应的第一，第二，第三或第四存储器单元串之一的第二端子。

    Semiconductor memory with vertical memory transistors and method for fabricating it
    57.
    发明授权
    Semiconductor memory with vertical memory transistors and method for fabricating it 有权
    具有垂直存储晶体管的半导体存储器及其制造方法

    公开(公告)号：US07265413B2

    公开(公告)日：2007-09-04

    申请号：US11073205

    申请日：2005-03-05

    申请人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    发明人： Franz Hofmann ,  Erhard Landgraf ,  Richard Johannes Luyken ,  Thomas Schulz ,  Michael Specht

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7923 ,  H01L29/7926

    摘要： The invention relates to a semiconductor memory having a multiplicity of memory cells and a method for forming the memory cells. The semiconductor memory generally includes a semiconductor layer arranged on a substrate surface that includes a normally positioned step between a deeper region and a higher region. The semiconductor memory further includes doped contact regions, channel regions, a trapping layer arranged on a gate oxide layer, and at least one gate electrode. The method for forming the memory cells includes patterning a semiconductor layer to form a deeper semiconductor region and a higher semiconductor region having a step positioned between the regions. The method further includes forming a first oxide layer and a trapping layer, and then removing portions of the trapping layer and the first oxide layer and applying a second oxide layer at least regions of a doped region, the trapping layer, and the step area, and applying a gate electrode to the second oxide layer and doping, at least in regions, of the deeper semiconductor region and the higher semiconductor region to form a deeper contact region and a higher contact region.

    摘要翻译： 本发明涉及具有多个存储单元的半导体存储器和用于形成存储单元的方法。 半导体存储器通常包括布置在衬底表面上的半导体层，其包括较深区域和较高区域之间的正常定位的台阶。 半导体存储器还包括掺杂接触区域，沟道区域，布置在栅极氧化物层上的俘获层和至少一个栅电极。 形成存储单元的方法包括图案化半导体层以形成较深的半导体区域和具有位于该区域之间的台阶的较高半导体区域。 该方法还包括形成第一氧化物层和俘获层，然后去除俘获层和第一氧化物层的部分，并且至少在掺杂区域，俘获层和台阶区域的区域上施加第二氧化物层， 以及向所述第二氧化物层施加栅电极，并且至少在所述较深半导体区域和所述较高半导体区域的区域中掺杂以形成更深的接触区域和更高的接触区域。

    Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement
    58.
    发明申请
    Production method for a FinFET transistor arrangement, and corresponding FinFET transistor arrangement 有权

    公开(公告)号：US20070158756A1

    公开(公告)日：2007-07-12

    申请号：US11649470

    申请日：2007-01-04

    申请人： Lars Dreeskornfeld ,  Franz Hofmann ,  Johannes Luyken ,  Michael Specht

    发明人： Lars Dreeskornfeld ,  Franz Hofmann ,  Johannes Luyken ,  Michael Specht

    IPC分类号： H01L29/76

    CPC分类号： H01L21/823412 ,  H01L21/823437 ,  H01L29/66818 ,  H01L29/7851

    摘要： The present invention provides a production method for a FinFET transistor arrangement, and a corresponding FinFET transistor arrangement. The method comprises the following steps: provision of a substrate (106, 108); formation of an active region (1) on the substrate, said active region having a source region (114), a drain region (116) and an intervening fin-like channel region (113b′; 113b″) for each individual FinFET transistor; formation of a gate dielectric (11) and a gate region (13, 14, 15) over the fin-like channel region (113b′; 113b″) for each individual FinFET transistor; the formation of the fin-like channel region (113b′; 113b″) having the following steps: formation of a hard mask (S1-S4) on the active region (1), said hard mask having a pad oxide layer (30), an overlying pad nitride layer (50) and nitride sidewall spacers (7); anisotropic etching of the active layer (1) using the hard mask (S1-S4) for the formation of STI trenches (G1-G5); filling of the STI trenches (G1-G5) with an STI oxide filling (9); polishing-back of the STI oxide filling (9) as far as the top side of the hard mask (S1-S4); etching-back of the polished-back STI oxide filling (9) as far as a residual height (h′) in the STI trenches (G1-G5); selective removal of the pad nitride layer (50) and the nitride sidewall spacers (7) with respect to the pad oxide layer (30), the etched-back STI oxide filling (9) and the active region (1) for the formation of a modified hard mask (S1′-S4′); anisotropic etching of the active layer (1) using the modified hard mask (S1′-S4′) for the formation of widened STI trenches (G1′-G5′), the fin-like channel regions (113b′; 113b″) of the active region (1) remaining for each individual FinFET transistor.

    Semiconductor memory device
    60.
    发明申请
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US20060267084A1

    公开(公告)日：2006-11-30

    申请号：US11139976

    申请日：2005-05-31

    申请人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele ,  Johannes Luyken

    发明人： Wolfgang Rosner ,  Franz Hofmann ,  Michael Specht ,  Martin Stadele ,  Johannes Luyken

    IPC分类号： H01L29/76

    CPC分类号： H01L27/108 ,  H01L27/10802 ,  H01L27/1203 ,  H01L29/7393

    摘要： A semiconductor memory device comprises a plurality of memory cells, each memory cell having a respective transistor. The transistor comprises a transistor body of a first conductivity type, a drain area and a source area each having a second conductivity type, wherein said drain area and source area are embedded in the transistor body on a first surface of said transistor body, a gate structure having a gate dielectric layer and a gate electrode. Said gate structure is arranged between said drain area and said source area. An emitter area of said first conductivity type is provided wherein said emitter area is arranged on top of said drain area.

    摘要翻译： 半导体存储器件包括多个存储单元，每个存储单元具有相应的晶体管。 晶体管包括第一导电类型的晶体管体，漏极区域和源极区域，每个具有第二导电类型，其中所述漏极区域和源极区域嵌入在所述晶体管本体的第一表面上的晶体管本体中，栅极 具有栅极电介质层和栅电极的结构。 所述栅极结构布置在所述漏极区域和所述源极区域之间。 提供了所述第一导电类型的发射极区域，其中所述发射极区域布置在所述漏极区域的顶部。