Abstract:
Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.
Abstract:
A method includes receiving a first element of a Galois Field of order qm, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qm and an integer p, where p is a prime number which divides qm−1. The second element z is raised to a pth power to form a third element. If the third element equals the first element, the second element multiplied by a pth root of unity raised to a respective power selected from a set of integers between 0 and p−1 is output as at least one root of the first element.
Abstract:
Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.
Abstract:
A method for data storage includes accepting data for storage in an array of memory cells, which are arranged in rows associated with respective word lines. Data is stored in one or more memory cells of the array using one or more programming levels. In response to a determination that a first memory cell of the one or more memory cells is subject to distortion, a second memory cell may be programmed to a predetermined programming level.
Abstract:
A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.
Abstract:
A method for decoding includes receiving channel inputs for respective bits of a super code word that includes at least first and second component code words having a shared group of bits. At least the first and second component code words are iteratively decoded, and, in response to recognizing that the first and second component code words contain errors only within the shared group of bits, the first and second component code words are jointly decoded.
Abstract:
A method includes accepting a definition of a mother Error Correction Code (ECC) that is represented by a set of parity check equations and includes first code words, and a definition of a punctured ECC that includes second code words and is derived from the mother ECC by removal of one or more of the parity check equations and removal of one or more punctured check symbols selected from among check symbols of the first code words. A mother decoder, which is designed to decode the mother ECC by exchanging messages between symbol nodes and check nodes in accordance with a predefined interconnection scheme that represents the mother ECC, is provided. An input code word of the punctured ECC is decoded using the mother decoder by initializing one or more of the symbol nodes and controlling one or more of the messages, and while retaining the interconnection scheme.
Abstract:
A method includes decoding a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations, such that each iteration involves processing of multiple variable nodes. For one or more selected variable nodes, a count of the check equations that are defined over one or more variables held respectively by the one or more selected variable nodes is evaluated, and, when the count meets a predefined skipping criterion, the one or more selected variable nodes are omitted from a given iteration in the sequence.
Abstract:
A method for data storage includes, in a first programming phase, storing first data in a group of memory cells by programming the memory cells in the group to a set of initial programming levels. In a subsequent second programming phase, second data is stored in the group by identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels, and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels. The memory cells to which the second data was programmed are recognized by reading only a partial subset of the first data. The second data is read from the recognized memory cells.
Abstract:
A method for data storage includes providing a mapping of data pages to physical pages, in which each physical page holds a non-integer number of the data pages, for storage of data in at least one memory block, including a plurality of the physical pages, in a memory device. The data pages that are mapped to the memory block are partitioned into groups, such that failure of any memory unit, which consists of a predefined number of the physical pages in the memory device, will produce errors in no more than one data page in each group. The data pages is stored in the physical pages of the memory block in accordance with the mapping, while a redundant storage scheme is applied among the data pages of each group.