Configurable Encoder for Cyclic Error Correction Codes
    51.
    发明申请
    Configurable Encoder for Cyclic Error Correction Codes 有权
    用于循环纠错码的可配置编码器

    公开(公告)号:US20130272356A1

    公开(公告)日:2013-10-17

    申请号:US13920157

    申请日:2013-06-18

    Applicant: Apple Inc.

    Inventor: Micha Anholt

    Abstract: Apparatus for encoding includes a first processing stage, which is configured to filter input data with a first set of coefficients belonging to a first generator polynomial representing a first ECC, to produce a first output. A second processing stage is configured to filter the first output using a second set of coefficients belonging to a quotient polynomial, which is defined as a quotient of a second generator polynomial, representing a second ECC, divided by the first generator polynomial, to produce a second output. Ancillary circuitry has first and second operational modes and is coupled to the first and second processing stages so as to generate a first redundancy output corresponding to the first ECC based on the first output when operating in the first mode, and to generate a second redundancy output corresponding to the second ECC based on the second output when operating in the second mode.

    Abstract translation: 用于编码的装置包括第一处理级,其被配置为使用属于表示第一ECC的第一生成多项式的第一组系数来过滤输入数据,以产生第一输出。 第二处理阶段被配置为使用属于商多项式的第二组系数来对第一输出进行过滤,商系多项式被定义为表示第二ECC的第二生成多项式的商除以第一生成多项式,以产生 第二输出。 辅助电路具有第一和第二操作模式,并且耦合到第一和第二处理级,以便当在第一模式下操作时,基于第一输出产生对应于第一ECC的第一冗余输出,并产生第二冗余输出 在第二模式下操作时,基于第二输出对应于第二ECC。

    Cubic root of a galois field element

    公开(公告)号:US09804828B2

    公开(公告)日:2017-10-31

    申请号:US14551110

    申请日:2014-11-24

    Applicant: APPLE INC.

    CPC classification number: G06F7/724 G06F7/552 G06F7/5525 G06F2207/5526

    Abstract: A method includes receiving a first element of a Galois Field of order qm, where q is a prime number and m is a positive integer. The first element is raised to a predetermined power so as to form a second element z, wherein the predetermined power is a function of qm and an integer p, where p is a prime number which divides qm−1. The second element z is raised to a pth power to form a third element. If the third element equals the first element, the second element multiplied by a pth root of unity raised to a respective power selected from a set of integers between 0 and p−1 is output as at least one root of the first element.

    High-performance ECC decoder
    53.
    发明授权
    High-performance ECC decoder 有权
    高性能ECC解码器

    公开(公告)号:US09535788B2

    公开(公告)日:2017-01-03

    申请号:US14821124

    申请日:2015-08-07

    Applicant: Apple Inc.

    Abstract: Methods for Error Correction Code (ECC) decoding include producing syndromes from a set of bits, which represent data that has been encoded with the ECC. An Error Locator Polynomial (ELP) is generated based on the syndromes. At least some of the ELP roots are identified, and the errors indicated by these roots are corrected. Each syndrome may be produced by applying to the bits vector operations in a vector space. Each syndrome is produced by applying vector operations using a different basis of the vector space. The ELP may be evaluated on a given field element by operating on ELP coefficients using serial multipliers, wherein each serial multiplier performs a sequence of multiplication cycles and produces an interim result in each cycle. Responsively to detecting at least one interim result indicating that the given element is not an ELP root, the multiplication cycles are terminated before completion of the sequence.

    Abstract translation: 用于纠错码(ECC)解码的方法包括从表示已经用ECC编码的数据的一组位产生综合征。 错误定位器多项式(ELP)是基于综合征产生的。 识别至少一些ELP根,并校正由这些根指示的错误。 可以通过应用向量空间中的比特向量操作来产生每个综合征。 通过使用向量空间的不同基础应用向量运算来产生每个综合征。 可以通过使用串行乘法器对ELP系数进行操作,在给定的场元件上评估ELP,其中每个串行乘法器执行乘法周期序列,并在每个周期中产生中间结果。 响应于检测至少一个中期结果,指示给定的元素不是ELP根,在完成序列之前终止乘法循环。

    Power-optimized decoding of linear codes

    公开(公告)号:US09337955B2

    公开(公告)日:2016-05-10

    申请号:US13965508

    申请日:2013-08-13

    Applicant: Apple Inc.

    Abstract: A method includes accepting an input code word, which was produced by encoding data with an Error Correction Code (ECC), for decoding by a hardware-implemented ECC decoder. The input code word is pre-processed to produce a pre-processed code word, such that a first number of bit transitions that occur in the hardware-implemented ECC decoder while decoding the pre-processed code word is smaller than a second number of the bit transitions that would occur in the ECC decoder in decoding the input code word. The pre-processed code word is decoded using the ECC decoder, and the data is recovered from the decoded pre-processed code word.

    Efficient LDPC codes
    57.
    发明授权
    Efficient LDPC codes 有权
    高效的LDPC码

    公开(公告)号:US09075738B2

    公开(公告)日:2015-07-07

    申请号:US14090498

    申请日:2013-11-26

    Applicant: Apple Inc.

    Abstract: A method includes accepting a definition of a mother Error Correction Code (ECC) that is represented by a set of parity check equations and includes first code words, and a definition of a punctured ECC that includes second code words and is derived from the mother ECC by removal of one or more of the parity check equations and removal of one or more punctured check symbols selected from among check symbols of the first code words. A mother decoder, which is designed to decode the mother ECC by exchanging messages between symbol nodes and check nodes in accordance with a predefined interconnection scheme that represents the mother ECC, is provided. An input code word of the punctured ECC is decoded using the mother decoder by initializing one or more of the symbol nodes and controlling one or more of the messages, and while retaining the interconnection scheme.

    Abstract translation: 一种方法包括接受由一组奇偶校验方程表示的母体误差校正码(ECC)的定义,并且包括第一码字和包括第二码字并从母体ECC导出的穿孔ECC的定义 通过去除一个或多个奇偶校验方程和从第一码字的检查符号中选出的一个或多个穿孔校验符号的去除。 提供了一种母版解码器,其被设计为通过根据表示母ECC的预定互连方案在符号节点和校验节点之间交换消息来解码母ECC。 通过初始化符号节点中的一个或多个并控制消息中的一个或多个,同时保留互连方案,使用母版解码器解码穿孔ECC的输入码字。

    DECODER WITH SELECTIVE ITERATION SCHEDULING
    58.
    发明申请
    DECODER WITH SELECTIVE ITERATION SCHEDULING 有权
    具有选择性迭代调度的解码器

    公开(公告)号:US20150180511A1

    公开(公告)日:2015-06-25

    申请号:US14138809

    申请日:2013-12-23

    Applicant: Apple Inc.

    CPC classification number: H03M13/1111 H03M13/1128 H03M13/114 H03M13/3715

    Abstract: A method includes decoding a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations, such that each iteration involves processing of multiple variable nodes. For one or more selected variable nodes, a count of the check equations that are defined over one or more variables held respectively by the one or more selected variable nodes is evaluated, and, when the count meets a predefined skipping criterion, the one or more selected variable nodes are omitted from a given iteration in the sequence.

    Abstract translation: 一种方法包括通过执行一系列迭代来解码纠错码(ECC)的代码字,其可由一组检验方程表示,使得每次迭代涉及多个可变节点的处理。 对于一个或多个选定的变量节点,评估在一个或多个所选变量节点分别保存的一个或多个变量上定义的检验方程的计数,并且当该计数满足预定的跳过标准时,该一个或多个 在序列中给定的迭代中省略了选定的变量节点。

    Data Storage Management in Analog Memory Cells Using a Non-Integer Number of Bits Per Cell
    59.
    发明申请
    Data Storage Management in Analog Memory Cells Using a Non-Integer Number of Bits Per Cell 有权
    使用非整数每个单元的位数模拟存储单元中的数据存储管理

    公开(公告)号:US20150179265A1

    公开(公告)日:2015-06-25

    申请号:US14135881

    申请日:2013-12-20

    Applicant: Apple Inc.

    Abstract: A method for data storage includes, in a first programming phase, storing first data in a group of memory cells by programming the memory cells in the group to a set of initial programming levels. In a subsequent second programming phase, second data is stored in the group by identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels, and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels. The memory cells to which the second data was programmed are recognized by reading only a partial subset of the first data. The second data is read from the recognized memory cells.

    Abstract translation: 一种用于数据存储的方法包括在第一编程阶段中通过将组中的存储器单元编程为一组初始编程级别来将第一数据存储在一组存储器单元中。 在随后的第二编程阶段,通过将在第一编程阶段中编程的组中的存储器单元识别为初始编程级的预定义部分子集中的相应级别,并且仅编程所识别的存储器,将第二数据存储在组中 具有第二数据的单元,以便将所识别的存储器单元中的至少一些设置为与初始编程电平不同的一个或多个附加编程电平。 通过仅读取第一数据的部分子集来识别第二数据被编程到的存储器单元。 从识别的存储器单元读取第二数据。

    PROTECTION AGAINST WORD LINE FAILURE IN MEMORY DEVICES
    60.
    发明申请
    PROTECTION AGAINST WORD LINE FAILURE IN MEMORY DEVICES 审中-公开
    对存储器件中的字线故障进行保护

    公开(公告)号:US20150128010A1

    公开(公告)日:2015-05-07

    申请号:US14595578

    申请日:2015-01-13

    Applicant: Apple Inc.

    Abstract: A method for data storage includes providing a mapping of data pages to physical pages, in which each physical page holds a non-integer number of the data pages, for storage of data in at least one memory block, including a plurality of the physical pages, in a memory device. The data pages that are mapped to the memory block are partitioned into groups, such that failure of any memory unit, which consists of a predefined number of the physical pages in the memory device, will produce errors in no more than one data page in each group. The data pages is stored in the physical pages of the memory block in accordance with the mapping, while a redundant storage scheme is applied among the data pages of each group.

    Abstract translation: 一种用于数据存储的方法包括提供数据页到物理页面的映射,其中每个物理页面保存非整数个数据页,用于将数据存储在至少一个存储块中,包括多个物理页面 ,在存储设备中。 映射到存储器块的数据页被划分成组,使得由存储器设备中的预定数量的物理页组成的任何存储器单元的故障将在每个不超过一个数据页面中产生错误 组。 根据映射将数据页存储在存储器块的物理页面中,同时在每个组的数据页之间应用冗余存储方案。

Patent Agency Ranking