公开(公告)号：US5292683A

公开(公告)日：1994-03-08

申请号：US71752

申请日：1993-06-09

申请人： Charles H. Dennison ,  Trung T. Doan

发明人： Charles H. Dennison ,  Trung T. Doan

IPC分类号： H01L21/76 ,  H01L21/108 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  H01L21/304

CPC分类号： H01L27/10852 ,  H01L21/76224 ,  H01L21/823481 ,  Y10S148/05

摘要： A semiconductor processing device isolation method includes: a) providing non-LOCOS insulating device isolation blocks by trench and refill technique on a substrate to define recessed moat volume therebetween; b) providing gate dielectric within the moat volume; c) providing a layer of electrically conductive material over the substrate and gate dielectric to a thickness sufficient to completely fill the moat volume between adjacent isolation blocks; d) chemical-mechanical polishing the layer of electrically conductive material to provide a planarized upper electrically conductive material surface; e) photopatterning and etching the layer of electrically conductive material to provide an electrically conductive runner which overlies a plurality of the isolation blocks and to selectively remove the electrically conductive material from within selected regions of moat volume to define field effect transistor gates within the moat volume; and f) providing conductivity enhancing impurity through the selected regions of moat volume into the substrate to define source/drain regions adjacent the field effect transistor gates. The invention also includes an array of memory integrated circuitry.

摘要翻译： 半导体处理器件隔离方法包括：a）通过沟槽和再填充技术在衬底上提供非LOCOS绝缘器件隔离块，以在其间限定凹陷的沟槽体积; b）在护城河容积内提供栅极电介质; c）在衬底和栅极电介质上提供一层导电材料，其厚度足以完全填充相邻隔离块之间的护城河体积; d）化学机械抛光导电材料层以提供平坦化的上导电材料表面; e）对导电材料层进行光图案化和蚀刻，以提供覆盖在多个隔离块上的导电浇道，并且选择性地从导流槽体积的选定区域内去除导电材料，以在护城河体积内限定场效应晶体管栅极 ; 以及f）通过所选择的沟槽体积的区域提供导电性增强杂质到衬底中以限定与场效应晶体管栅极相邻的源极/漏极区域。 本发明还包括一组存储器集成电路。

公开(公告)号：US5234855A

公开(公告)日：1993-08-10

申请号：US633595

申请日：1990-12-21

申请人： Howard E. Rhodes ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Gurtej S. Sandhu

发明人： Howard E. Rhodes ,  Hiang C. Chan ,  Charles H. Dennison ,  Yauh-Ching Liu ,  Pierre C. Fazan ,  Gurtej S. Sandhu

IPC分类号： H01L21/02 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  H01L27/10817 ,  H01L28/87 ,  H01L28/91

摘要： A stacked comb spacer capacitor (SCSC) using a modified stacked capacitor storage cell fabrication process. The SCSC is made up of polysilicon structure, having a spiked v-shaped (or comb-shaped) cross-section, located at a buried contact and extending to an adjacent storage node overlaid by polysilicon with a dielectric sandwiched in between. The creation of the spiked polysilicon structure increases storage capability 50% without enlarging the surface area defined for a normal buried digit line stacked capacitor cell. Removing the dielectric residing under the backside of the storage node cell plate and filling that area with polysilicon increases storage capacity by an additional 50% or more.

摘要翻译： 使用改进的堆叠电容器存储单元制造工艺的堆叠梳状间隔电容器（SCSC）。 SCSC由多晶硅结构组成，具有加深的V形（或梳状）横截面，位于掩埋接触处，并延伸到由多晶硅覆盖的相邻存储节点和介于其间的电介质。 掺杂多晶硅结构的产生增加了存储能力50％，而不会扩大为正常埋地数字线叠层电容器单元定义的表面积。 去除位于存储节点单元板背面的电介质并用多晶硅填充该区域将存储容量提高了50％以上。

公开(公告)号：US5229326A

公开(公告)日：1993-07-20

申请号：US902374

申请日：1992-06-23

申请人： Charles H. Dennison ,  Guy T. Blalock

发明人： Charles H. Dennison ,  Guy T. Blalock

IPC分类号： H01L21/28 ,  H01L21/60 ,  H01L21/768 ,  H01L23/485 ,  H01L23/522

CPC分类号： H01L21/76897 ,  H01L23/485 ,  H01L23/5226 ,  H01L2924/0002

摘要： A semiconducting processing method for making electrical contacts with an active area in sub-micron geometries includes: (a) providing a pair of conductive runners on a semiconductor wafer; (b) providing insulative spacers on the sides of the conductive runners wherein adjacent spacers are spaced a selected distance apart at a selected location on the wafer; (c) providing an active area between the conductive runners at the selected location; (d) providing an oxide layer over the active area and conductive runners; (e) providing a planarized nitride layer atop the oxide layer; (f) patterning and etching the nitride layer selectively relative to the oxide layer to define a first contact opening therethrough, wherein the first contact opening has an aperture width at the nitride layer upper surface which is greater than the selected distance between the insulative spacers; (g) etching the oxide layer within the first contact opening to expose the active area; (h) providing a polysilicon plug within the first contact opening over the exposed active areas; (i) providing an insulating layer over the nitride layer and the polysilicon plug; (j) patterning and etching the insulating layer to form a second contact opening to and exposing the polysilicon plug; and (k) providing a conductive layer over the insulating layer and into the second opening to electrically contact the polysilicon plug. A semiconductor device having buried landing plugs of approximately uniform height across the wafer is also described.

摘要翻译： 用于与亚微米几何形状的有源区进行电接触的半导体处理方法包括：（a）在半导体晶片上提供一对导电流道; （b）在导电流道的侧面上设置绝缘间隔物，其中相邻的间隔物在晶片上的选定位置间隔一段距离; （c）在所选位置的导电流道之间提供有效区域; （d）在有源区域和导电流道上提供氧化物层; （e）在氧化物层的顶部提供平坦化的氮化物层; （f）相对于所述氧化物层选择性地图案化和蚀刻所述氮化物层以限定穿过其中的第一接触开口，其中所述第一接触开口在所述氮化物层上表面处具有大于所述绝缘间隔物之间​​的所选距离的孔径宽度; （g）蚀刻第一接触开口内的氧化物层以暴露有源区; （h）在所述暴露的有源区域之上的所述第一接触开口内提供多晶硅插塞; （i）在氮化物层和多晶硅插塞上方提供绝缘层; （j）图案化和蚀刻绝缘层以形成第二接触开口并暴露多晶硅插塞; 和（k）在绝缘层上提供导电层并进入第二开口以电接触多晶硅插塞。 还描述了具有跨越晶片大致均匀高度的埋地层塞的半导体器件。

公开(公告)号：US5170233A

公开(公告)日：1992-12-08

申请号：US722854

申请日：1991-06-27

申请人： Yauh-Ching Liu ,  Pierre C. Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Howard E. Rhodes

发明人： Yauh-Ching Liu ,  Pierre C. Fazan ,  Hiang C. Chan ,  Charles H. Dennison ,  Howard E. Rhodes

IPC分类号： H01L21/02 ,  H01L27/108 ,  H01L29/92

CPC分类号： H01L27/10817 ,  H01L28/87 ,  H01L28/90

摘要： A method of fabricating a semiconductor wafer comprises providing an electrically conductive area on a semiconductor wafer. Multiple alternating layers of first and second materials are provided atop the wafer. The first and second materials need be selectively etchable relative to one another. The multiple layers are etched and the electrically conductive area upwardly exposed to define exposed edges of the multiple layers projecting upwardly from the electrically conductive area. One of the first or second materials is selectively isotropically etched relative to the other to produce indentations which extend generally laterally into the exposed edges of the multiple layers. A layer of electrically conductive material is applied atop the wafer and electrically conductive area, and fills the exposed edge indentations. The electrically conductive material is etched to leave conductive material extending upwardly from the electrically conductive area adjacent the multiple layer edges and within the indentations. The multiple layers are etched from the wafer to leave upwardly projecting conductive material having lateral projections extending therefrom. Such material is used to form the lower plate of a capacitor.

摘要翻译： 制造半导体晶片的方法包括在半导体晶片上提供导电区域。 将第一和第二材料的多个交替层设置在晶片顶部。 第一和第二材料需要相对于彼此可选择性地蚀刻。 蚀刻多个层，并且导电区域向上暴露以限定从导电区域向上突出的多个层的暴露边缘。 第一或第二材料之一相对于另一材料选择性地各向同性地蚀刻，以产生大致横向延伸到多层的暴露边缘的凹痕。 将一层导电材料施加在晶片和导电区域顶部，并填充暴露的边缘凹陷。 蚀刻导电材料以留下从邻近多层边缘和凹陷内的导电区域向上延伸的导电材料。 从晶片上蚀刻多层以留下向上突出的具有从其延伸的侧向突起的导电材料。 这种材料用于形成电容器的下板。

公开(公告)号：US20130270502A1

公开(公告)日：2013-10-17

申请号：US13910237

申请日：2013-06-05

申请人： Charles H. Dennison ,  Stephen J. Hudgens

发明人： Charles H. Dennison ,  Stephen J. Hudgens

IPC分类号： H01L45/00

CPC分类号： H01L45/065 ,  G11C13/0004 ,  H01L27/2427 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  Y10S977/754

摘要： In accordance with some embodiments, a phase change memory may be formed in which the thermal conductivity in the region outside the programmed volume of phase change material is reduced. This may reduce the power consumption of the resulting phase change memory. The reduction in power consumption may be achieved by forming distinct layers of phase change material that have little or no mixing between them outside the programmed volume. In one embodiment, a face centered cubic chalcogenide structure may be utilized.

摘要翻译： 根据一些实施例，可以形成相变存储器，其中减少了编程体积相变材料之外的区域中的热导率。 这可能会降低所得相变存储器的功耗。 功耗的降低可以通过在编程体积之外形成很少或不混合的相变材料的不同层来实现。 在一个实施方案中，可以使用面心立方硫属元素化合物结构。

公开(公告)号：US07917692B2

公开(公告)日：2011-03-29

申请号：US12069812

申请日：2008-02-12

申请人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

发明人： Brent Keeth ,  Brian M. Shirley ,  Charles H. Dennison ,  Kevin J. Ryan

IPC分类号： G06F12/00

CPC分类号： G06F12/0893 ,  G06F12/0846 ,  G06F12/0897 ,  G11C7/1006 ,  G11C7/1042 ,  G11C11/406 ,  G11C11/409 ,  G11C15/043

摘要： A cache memory system and method includes a DRAM having a plurality of banks, and it also includes 2 SRAMs each having a capacity that is equal to the capacity of each bank of the DRAM. In operation, data read from a bank of the DRAM are stored in one of the SRAMs so that repeated hits to that bank are cached by reading from the SRAM. In the event of a write to a bank that is being refreshed, the write data are stored in one of the SRAMs. After the refresh of the bank has been completed, the data stored in the SRAM are transferred to the DRAM bank. A subsequent read or write to a second DRAM bank undergoing refresh and occurring during the transfer of data from an SRAM to the DRAM is stored in either the second bank or the other SRAM.

摘要翻译： 高速缓冲存储器系统和方法包括具有多个存储体的DRAM，并且它们还包括两个SRAM，每个SRAM的容量等于DRAM的每个存储体的容量。 在操作中，从DRAM的存储体读出的数据被存储在一个SRAM中，从而通过从SRAM读取来缓存对该存储体的重复命中。 在写入正在刷新的存储体的情况下，写入数据被存储在一个SRAM中。 在银行刷新完成之后，存储在SRAM中的数据被传送到DRAM存储体。 在从SRAM到DRAM的数据传输期间经历刷新并发生的第二DRAM组的后续读或写存储在第二存储体或其它SRAM中。

公开(公告)号：US20110031460A1

公开(公告)日：2011-02-10

申请号：US12908406

申请日：2010-10-20

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L45/00

CPC分类号： H01L45/126 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

摘要： The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

摘要翻译： 本发明提供了一种基于可变电阻材料存储元件的存储单元，其包括具有柱结构的存取装置，所述柱结构还可包括保护侧壁层。 支柱存取装置选择并隔离其他存储器阵列单元的存储单元，并且适于将形成在其上的任何存储元件自对准，并将适当的编程电流传送到存储元件。 柱结构由堆叠在字线上方和存储元件下方的一个或多个访问器件层形成。 可选择性地在柱结构内形成可选的电阻层，以最小化存取器件层和存储元件中的电阻。 柱式存取装置可以是二极管，晶体管，Ovonic阈值开关或能够调节流向上覆可编程存储器材料的电流的其他装置。

公开(公告)号：US07838341B2

公开(公告)日：2010-11-23

申请号：US12075913

申请日：2008-03-14

申请人： Charles H. Dennison

发明人： Charles H. Dennison

IPC分类号： H01L21/82

CPC分类号： H01L45/126 ,  H01L27/2409 ,  H01L27/2436 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1683

摘要： The invention provides a memory cell based on variable resistance material memory element that includes an access device having a pillar structure that may also include a protective sidewall layer. The pillar access device selects and isolates the memory cell from other memory array cells and is adapted to both self-align any memory element formed thereon, and to deliver suitable programming current to the memory element. The pillar structure is formed from one or more access device layers stacked above a wordline and below the memory element. Optional resistive layers may be selectively formed within the pillar structure to minimize resistance in the access device layer and the memory element. The pillar access device may be a diode, transistor, Ovonic threshold switch or other device capable of regulating current flow to an overlying programmable memory material.

摘要翻译： 本发明提供了一种基于可变电阻材料存储元件的存储单元，其包括具有柱结构的存取装置，所述柱结构还可包括保护侧壁层。 支柱存取装置选择并隔离其他存储器阵列单元的存储单元，并且适于将形成在其上的任何存储元件自对准，并将适当的编程电流传送到存储元件。 柱结构由堆叠在字线上方和存储元件下方的一个或多个访问器件层形成。 可选择性地在柱结构内形成可选的电阻层，以最小化存取器件层和存储元件中的电阻。 柱式存取装置可以是二极管，晶体管，Ovonic阈值开关或能够调节流向上覆可编程存储器材料的电流的其他装置。

公开(公告)号：US20100163825A1

公开(公告)日：2010-07-01

申请号：US12346507

申请日：2008-12-30

申请人： Charles H. Dennison ,  George A. Gordon ,  John M. Peters

发明人： Charles H. Dennison ,  George A. Gordon ,  John M. Peters

IPC分类号： H01L47/00 ,  H01L45/00

CPC分类号： H01L45/06 ,  H01L27/2427 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1683

摘要： A phase change memory cell may be formed with a pair of chalcogenide phase change layers that are separated by a breakdown layer. The breakdown layer may be broken down prior to use of the memory so that a conductive breakdown point is defined within the breakdown layer. In some cases, the breakdown point may be well isolated from the surrounding atmosphere, reducing heat losses and decreasing current consumption. In addition, in some cases, the breakdown point may be well isolated from overlying and underlying electrodes, reducing issues related to contamination. The breakdown point may be placed between a pair of chalcogenide layers with the electrodes outbound of the two chalcogenide layers.

摘要翻译： 相变存储单元可以由被击穿层分开的一对硫族化物相变层形成。 在使用存储器之前可以将击穿层分解，使得在击穿层内限定导电击穿点。 在某些情况下，故障点可能与周围大气良好隔离，减少热损失和降低电流消耗。 此外，在某些情况下，击穿点可能与上覆电极和下层电极很好地隔离，从而减少与污染有关的问题。 击穿点可以放置在一对硫族化物层之间，其中两个硫族化物层的电极出发。

公开(公告)号：US07572666B2

公开(公告)日：2009-08-11

申请号：US10438146

申请日：2003-05-13

申请人： Charles H. Dennison ,  Alice T. Wang ,  Kanaiyalal Chaturbhai Patel ,  Jenn C. Chow

发明人： Charles H. Dennison ,  Alice T. Wang ,  Kanaiyalal Chaturbhai Patel ,  Jenn C. Chow

IPC分类号： H01L21/00

CPC分类号： H01L27/1021 ,  H01L21/761 ,  H01L27/24

摘要： A method comprising forming a first dielectric layer over an electrode formed to a first contact point on a substrate, the electrode having a contact area; patterning the first dielectric layer into a body, a thickness of the first dielectric layer defining a side wall; forming at least one spacer along the side wall of the first dielectric body, the at least one spacer overlying a portion of the contact area; forming a second dielectric layer on the contact area; removing the at least one spacer; and forming a material comprising a second contact point to the contact area. An apparatus comprising a volume of programmable material; a conductor; and an electrode disposed between the volume of programmable material and the conductor, the electrode having a contact area coupled to the volume of programmable material.

摘要翻译： 一种方法，包括在形成于基底上的第一接触点的电极上形成第一介电层，所述电极具有接触面积; 将第一介电层图案化成体，第一介电层的厚度限定侧壁; 沿着所述第一电介质体的侧壁形成至少一个间隔物，所述至少一个间隔件覆盖所述接触区域的一部分; 在所述接触区域上形成第二电介质层; 去除所述至少一个间隔物; 以及形成包括接触区域的第二接触点的材料。 一种包括一定量的可编程材料的装置; 指挥 以及设置在所述可编程材料的体积和所述导体之间的电极，所述电极具有耦合到所述可编程材料的体积的接触面积。