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51.发明申请METHOD OF DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE 有权确定设计结构的停留力与移动颗粒相关的方法公开(公告)号：US20080163137A1
公开(公告)日：2008-07-03
申请号：US11618993
申请日：2007-01-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5009 , G06F2217/16
摘要： A method of determining a stopping power of a design structure with respect to a traveling particle. The method includes (i) providing design information of the design structure comprising a back-end-of-line layer which includes N interconnect layers, N being a positive integer, (ii) dividing each interconnect layer of the N interconnect layers into multiple pixels, and (iii) determining a first path of the traveling particle in a first interconnect layer of the N interconnect layers, (iv) identifying M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle, M being a positive integer, and (v) determining a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels.
摘要翻译： 确定设计结构相对于行进颗粒的停止力的方法。 该方法包括（i）提供设计结构的设计信息，该设计结构包括后端行层，其包括N个互连层，N为正整数，（ii）将N个互连层的每个互连层划分成多个像素 ，和（iii）确定所述N个互连层的第一互连层中的所述行进粒子的第一路径，（iv）识别所述行进粒子的所述第一路径上的所述第一互连层的所述多个像素的M个路径像素，M 作为正整数，以及（v）确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。
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公开(公告)号：US06685548B2
公开(公告)日：2004-02-03
申请号：US10424840
申请日：2003-04-29
IPC分类号： B24B722
摘要： Grooves are formed in a CMP pad by positioning the pad on a supporting surface with a working surface of the pad in spaced relation opposite to a router bit and at least one projecting stop member adjacent to the router bit, an outer end portion of the bit projecting beyond the stop. When the bit is rotated, relative axial movement between the bit and the pad causes the outer end portion of the bit to cut an initial recess in the pad. Relative lateral movement between the rotating bit and the pad then forms a groove which extends laterally away from the recess and has a depth substantially the same as that of the recess. The depths of the initial recess and the groove are limited by applying a vacuum to the working surface of the pad to keep it in contact with the stop member(s). Different lateral movements between the bit and the pad are used to form a variety of groove patterns, the depths of which are precisely controlled by the stop member(s). The grooves may be formed in the polishing surface and/or the rear opposite surface of the pad and passages may be provided for interconnecting the rear grooves with the polishing surface or the front grooves.
摘要翻译： 通过将衬垫定位在支撑表面上，使衬垫的工作表面与路由器刀片相对的间隔开的关系形成凹槽，并且至少一个与路由器刀头相邻的突出止动件，钻头的外端部分 突出超出停止。 当钻头旋转时，钻头和钻头之间的相对轴向运动使钻头的外端部分切割焊盘中的初始凹陷。 旋转钻头和垫之间的相对横向运动形成一个横向延伸离开凹槽并具有与凹槽基本相同的深度的凹槽。 通过将真空施加到垫的工作表面以使其与止动构件接触来限制初始凹部和凹槽的深度。 钻头和垫之间的不同横向运动用于形成各种凹槽图案，其深度由止动件精确地控制。 凹槽可以形成在抛光表面中和/或垫的后相对表面，并且可以设置通道用于将后槽与抛光表面或前槽相互连接。
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53.发明授权Multi-layer metal sandwich with taper and reduced etch bias and method for forming same 失效具有锥形和减少的蚀刻偏压的多层金属夹层及其形成方法
公开(公告)号：US5912506A
公开(公告)日：1999-06-15
申请号：US937349
申请日：1997-09-20
IPC分类号： G02F1/1362 , H01L23/498 , H01L23/538 , H01L23/48
CPC分类号： H01L23/538 , H01L23/49866 , G02F2001/13629 , H01L2924/0002
摘要： A multi-layer metal sandwich structure with taper and reduced etch bias formed on a substrate includes a first metal layer formed on the substrate and a second metal layer formed on the first metal layer. The width of the first metal layer is greater than the width of the second metal layer at the interface of the first metal layer and the second metal layer. The second metal layer has tapered side walls. The taper angle between each side wall and the intersection of the first and second metal layers is between 5.degree. and 90.degree.. The multi-layer metal sandwich may also include a third metal layer formed on the second metal layer.
摘要翻译： 在衬底上形成具有锥形和减少的蚀刻偏压的多层金属夹层结构包括形成在衬底上的第一金属层和形成在第一金属层上的第二金属层。 第一金属层的宽度大于第一金属层和第二金属层的界面处的第二金属层的宽度。 第二金属层具有锥形侧壁。 每个侧壁与第一和第二金属层的交点之间的锥角在5°和90°之间。 多层金属夹层物还可以包括形成在第二金属层上的第三金属层。
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公开(公告)号：US5171642A
公开(公告)日：1992-12-15
申请号：US638888
申请日：1991-01-08
IPC分类号： H01L21/48 , H01L23/498 , H05K1/09 , H05K3/16 , H05K3/38
CPC分类号： H01L21/4846 , H01L23/49866 , H01L2924/0002 , H05K1/09 , H05K3/16 , H05K3/388 , Y10T428/12528 , Y10T428/12743
摘要： A low copper concentration multilayered, device interconnect metallurgy, comprises an aluminum-copper (
摘要翻译： 低铜浓度多层器件互连冶金包括铝 - 铜（<2重量％铜）导体，其在其一个表面上形成由IVA金属形成的金属间化合物层和来自铝 - 铜导体的铝 。 金属间化合物形成为仅含有金属间化合物的单相化合物。
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公开(公告)号：US20120161300A1
公开(公告)日：2012-06-28
申请号：US13409643
申请日：2012-03-01
IPC分类号： H01L23/552
CPC分类号： H01L23/5329 , H01L23/556 , H01L2924/0002 , Y10S438/958 , Y10S438/967 , H01L2924/00
摘要： Methods of blocking ionizing radiation to reduce soft errors and resulting IC chips are disclosed. One embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming at least one back end of line (BEOL) dielectric layer including ionizing radiation blocking material therein. Another embodiment includes forming a front end of line (FEOL) for an integrated circuit (IC) chip; and forming an ionizing radiation blocking layer positioned in a back end of line (BEOL) of the IC chip. The ionizing radiation blocking material or layer absorbs ionizing radiation and reduces soft errors within the IC chip.
摘要翻译： 公开了阻止电离辐射以减少软错误的方法和产生的IC芯片。 一个实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及在其中形成包括其中的电离辐射阻挡材料的至少一个后端线（BEOL）电介质层。 另一实施例包括形成用于集成电路（IC）芯片的线路前端（FEOL）; 以及形成位于IC芯片的后端（BEOL）的电离辐射阻挡层。 电离辐射阻挡材料或层吸收电离辐射并减少IC芯片内的软误差。
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公开(公告)号：US20080225573A1
公开(公告)日：2008-09-18
申请号：US12130257
申请日：2008-05-30
IPC分类号： G11C11/00
CPC分类号： G11C11/4125 , Y10S257/903
摘要： A memory cell comprises a wordline, a first digital inverter with a first input and a first output, and a second digital inverter with a second input and a second output. Moreover, the memory cell further comprises a first feedback connection connecting the first output to the second input, and a second feedback connection connecting the second output to the first input. The first feedback connection comprises a first resistive element and the second feedback connection comprises a second resistive element. What is more, each digital inverter has an associated capacitance. The memory cell is configured such that reading the memory cell includes applying a read voltage pulse to the wordline. In addition, the first and second resistive elements are configured such that the first and second feedback connections have resistance-capacitance induced delays longer than the applied read voltage pulse.
摘要翻译： 存储单元包括字线，具有第一输入和第一输出的第一数字逆变器以及具有第二输入和第二输出的第二数字反相器。 此外，存储单元还包括将第一输出连接到第二输入的第一反馈连接和将第二输出连接到第一输入的第二反馈连接。 第一反馈连接包括第一电阻元件，第二反馈连接包括第二电阻元件。 更重要的是，每个数字逆变器都有相关的电容。 存储单元被配置为使得读取存储器单元包括将读取电压脉冲施加到字线。 此外，第一和第二电阻元件被配置为使得第一和第二反馈连接具有比施加的读取电压脉冲更长的电阻 - 电容感应延迟。
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57.发明授权Optimization of storage and power consumption with soft error predictor-corrector 失效使用软错误预测器校正器优化存储和功耗公开(公告)号：US06986078B2
公开(公告)日：2006-01-10
申请号：US10213690
申请日：2002-08-07
IPC分类号： G06F11/00
CPC分类号： H04L1/0001
摘要： A method and system for mitigating the impact of radiation induced in a data processor incorporating integrated circuits. The method comprises the steps of determining the location of the data processor, determining a set of radiation sources and intensities at that location, and estimating the soft error rate of the data processor as a function of the determined radiation intensities and geometric characteristics of said integrated circuits to provide an estimate value. The data processor is modified (either hardware or software) in response to the estimate value at times the estimate value exceeds a predetermined value.
摘要翻译： 一种用于减轻包含集成电路的数据处理器中引起的辐射影响的方法和系统。 该方法包括以下步骤：确定数据处理器的位置，确定该位置处的一组辐射源和强度，以及根据确定的所述集成的辐射强度和几何特性来估计数据处理器的软错误率 电路提供估计值。 数据处理器在估计值超过预定值的时候响应于估计值被修改（硬件或软件）。
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公开(公告)号：US06946716B2
公开(公告)日：2005-09-20
申请号：US10773434
申请日：2004-02-09
申请人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
发明人： Panayotis Constantinou Andricacos , Harikilia Deligianni , John Owen Dukovic , Daniel C. Edelstein , Wilma Jean Horkans , Chao-Kun Hu , Jeffrey Louis Hurd , Kenneth P. Rodbell , Cyprian Emeka Uzoh , Kwong-Hon Wong
IPC分类号： H01L21/288 , H01L21/768 , H01L29/00
CPC分类号： C25D3/38 , C25D5/022 , H01L21/2885 , H01L21/76877 , H01L21/76885
摘要： A process is described for the fabrication of submicron interconnect structures for integrated circuit chips. Void-free and seamless conductors are obtained by electroplating Cu from baths that contain additives and are conventionally used to deposit level, bright, ductile, and low-stress Cu metal. The capability of this method to superfill features without leaving voids or seams is unique and superior to that of other deposition approaches. The electromigration resistance of structures making use of CU electroplated in this manner is superior to the electromigration resistance of AlCu structures or structures fabricated using Cu deposited by methods other than electroplating.
摘要翻译： 描述了用于制造用于集成电路芯片的亚微米互连结构的过程。 通过从包含添加剂的浴中电镀Cu获得无空隙和无缝导体，并且通常用于沉积水平，光亮，延展性和低应力Cu金属。 这种方法在不留下空隙或接缝的情况下超量填充特征的能力是独一无二的，优于其他沉积方法。 以这种方式电镀Cu的结构的电迁移阻力优于AlCu结构或使用不是电镀方法沉积的Cu制造的结构的电迁移电阻。
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公开(公告)号：US06836106B1
公开(公告)日：2004-12-28
申请号：US10668561
申请日：2003-09-23
IPC分类号： G01R3126
CPC分类号： G11C29/56 , G01R31/2858 , G11C29/1201 , G11C2029/5602
摘要： A test circuit for testing semiconductors includes a plurality of at least first conductors and second conductors. The first and second conductors are operatively connected together by a plurality of conductive vias to form an open chain of alternating first and second conductors. A plurality of conductive taps are included, each of the taps being connected at a first end to a corresponding first conductor. The test circuit further includes a plurality of switching circuits, each of the switching circuits being operatively connected to a second end of a corresponding one of the conductive taps. Each of the switching circuits is configurable for selectively connecting the corresponding conductive tap to one of at least a first bus and a second bus in response to at least one control signal presented to the switching circuit, the first and second buses being connected to first and second bond pads, respectively.
摘要翻译： 用于测试半导体的测试电路包括多个至少第一导体和第二导体。 第一和第二导体通过多个导电通孔可操作地连接在一起以形成交替的第一和第二导体的开链。 包括多个导电抽头，每个抽头在第一端连接到对应的第一导体。 测试电路还包括多个开关电路，每个开关电路可操作地连接到对应的一个导电抽头的第二端。 响应于呈现给开关电路的至少一个控制信号，每个开关电路可配置为有选择地将对应的导电抽头连接到至少第一总线和第二总线中的一个，第一和第二总线连接到第一和第二总线 第二接合垫。
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公开(公告)号：US06792075B2
公开(公告)日：2004-09-14
申请号：US10225534
申请日：2002-08-21
申请人： Krzysztof J. Kozaczek , David S. Kurtz , Paul R. Moran , Roger I. Martin , Patrick W. Dehaven , Kenneth P. Rodbell , Sandra G. Malhotra
发明人： Krzysztof J. Kozaczek , David S. Kurtz , Paul R. Moran , Roger I. Martin , Patrick W. Dehaven , Kenneth P. Rodbell , Sandra G. Malhotra
IPC分类号： G01N2320
摘要： An apparatus and method for mapping film thickness of one or more textured polycrystalline thin films. Multiple sample films of known thickness are provided. Each sample film is irradiated by x-ray at a measurement point to generate a diffraction image that captures a plurality of diffraction arcs. Texture information (i.e., pole densities) of the sample film, is calculated based on incomplete pole figures collected on the diffraction image and used to correct the x-ray diffraction intensities from such sample. The corrected diffraction intensities are integrated for each sample film, and then used for constructing a calibration curve that correlates diffraction intensities with respective known film thickness of the sample films. The film thickness of a textured polycrystalline thin film of unknown thickness can therefore be mapped on such calibration curve, using a corrected and integrated diffraction intensity obtained for such thin film of unknown thickness.
摘要翻译： 一种用于映射一个或多个纹理多晶薄膜的膜厚度的装置和方法。 提供了已知厚度的多个样品膜。 每个样品膜在测量点用X射线照射，以产生捕获多个衍射弧的衍射图像。 基于在衍射图像上收集的不完全的极数计算样品膜的纹理信息（即极点密度），并用于校正这些样品的X射线衍射强度。 对每个样品膜整合校正的衍射强度，然后用于构建将衍射强度与样品膜的已知膜厚度相关联的校准曲线。 因此，可以使用未知厚度的薄膜获得的校正和积分的衍射强度，将这种具有未知厚度的纹理多晶薄膜的膜厚度映射到这种校准曲线上。
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