公开(公告)号：US06940089B2

公开(公告)日：2005-09-06

申请号：US10116559

申请日：2002-04-04

申请人： Zhiyuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri A. Antoniadis

发明人： Zhiyuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri A. Antoniadis

IPC分类号： H01L21/20 ,  H01L21/306 ,  H01L21/762 ,  H01L29/06 ,  H01L29/04 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072

CPC分类号： H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/30608

摘要： A method of fabricating a semiconductor structure. According to one aspect of the invention, on a first semiconductor substrate, a first compositionally graded Si1-xGex buffer is deposited where the Ge composition x is increasing from about zero to a value less than about 20%. Then a first etch-stop Si1-yGey layer is deposited where the Ge composition y is larger than about 20% so that the layer is an effective etch-stop. A second etch-stop layer of strained Si is then grown. The deposited layer is bonded to a second substrate. After that the first substrate is removed to release said first etch-stop Si1-yGey layer. The remaining structure is then removed in another step to release the second etch-stop layer. According to another aspect of the invention, a semiconductor structure is provided. The structure has a layer in which semiconductor devices are to be formed. The semiconductor structure includes a substrate, an insulating layer, a relaxed SiGe layer where the Ge composition is larger than approximately 15%, and a device layer selected from a group consisting of, but not limited to, strained-Si, relaxed Si1-yGey layer, strained S1-zGez layer, Ge, GaAs, III-V materials, and II-VI materials, where Ge compositions y and z are values between 0 and 1.

摘要翻译： 一种制造半导体结构的方法。 根据本发明的一个方面，在第一半导体衬底上沉积第一组分梯度的Si 1-x N Ge x N x缓冲层，其中Ge组合物x从约 零到小于约20％的值。 然后沉积第一蚀刻停止Si 1-y Ge层，其中Ge组分y大于约20％，使得该层是有效的蚀刻停止 。 然后生长第二蚀刻停止层的应变Si。 沉积层结合到第二衬底。 之后，去除第一衬底以释放所述第一蚀刻停止Si 1-y Ge层。 然后在另一步骤中除去剩余的结构以释放第二蚀刻停止层。 根据本发明的另一方面，提供一种半导体结构。 该结构具有要形成半导体器件的层。 半导体结构包括基底，绝缘层，Ge组分大于约15％的弛豫SiGe层，以及选自但不限于应变Si的弛豫Si

公开(公告)号：US06881632B2

公开(公告)日：2005-04-19

申请号：US10611739

申请日：2003-07-01

申请人： Eugene A. Fitzgerald ,  Nicole Gerrish

发明人： Eugene A. Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/10 ,  H01L21/336

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained surface layer on said relaxed Si1-xGex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-xGex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

摘要翻译： 一种制造CMOS反相器的方法，包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x Ge 2 x层的异质结构，以及在Si衬底上的应变表面层 所述松弛的Si 1-x Ge x层; 以及将pMOSFET和nMOSFET集成在所述异质结构中，其中所述pMOSFET的沟道和nMOSFET的沟道形成在应变表面层中。 另一个实施例提供一种制造集成电路的方法，该集成电路包括提供在Si衬底上具有Si衬底，弛豫的Si 1-x N x Ge x Si层的异质结构和应变 层在松弛的Si 1-x Ge层上; 以及在所述异质结构中形成p晶体管和n晶体管，其中所述应变层包括所述n晶体管和所述p晶体管的沟道，并且所述n晶体管和所述p晶体管在CMOS电路中互连。

公开(公告)号：US06864115B2

公开(公告)日：2005-03-08

申请号：US10268025

申请日：2002-10-09

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L21/205 ,  C30B25/02 ,  H01L21/20 ,  H01L21/00

CPC分类号： C30B25/02 ,  C30B29/40 ,  C30B29/42 ,  C30B29/52 ,  H01L21/02381 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262

摘要： A semiconductor structure and method of processing same including a substrate, a lattice-mismatched first layer deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, and a second layer deposited on the first layer with a greater lattice mismatch to the substrate than the first semiconductor layer. In another embodiment there is provided a semiconductor graded composition layer structure on a semiconductor substrate and a method of processing same including a semiconductor substrate, a first semiconductor layer having a series of lattice-mismatched semiconductor layers deposited on the substrate and annealed at a temperature greater than 100° C. above the deposition temperature, a second semiconductor layer deposited on the first semiconductor layer with a greater lattice mismatch to the substrate than the first semiconductor layer, and annealed at a temperature greater than 100° C. above the deposition temperature of the second semiconductor layer.

摘要翻译： 一种半导体结构及其处理方法，其包括：衬底，沉积在衬底上的晶格失配的第一层，并在高于淀积温度的大于100℃的温度下退火;以及沉积在第一层上的第二层， 与第一半导体层相比基板的晶格失配。 在另一个实施方案中，提供半导体衬底上的半导体梯度组合物层结构及其加工方法，其包括半导体衬底，第一半导体层，其具有沉积在衬底上并在较大温度下退火的一系列晶格失配的半导体层 比沉积温度高100℃;第二半导体层，其沉积在第一半导体层上，比第一半导体层具有比衬底更大的晶格失配，并且在高于第一半导体层的沉积温度 第二半导体层。

公开(公告)号：US06750130B1

公开(公告)日：2004-06-15

申请号：US09764177

申请日：2001-01-17

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L2128

CPC分类号： C30B25/02 ,  C30B29/40 ,  C30B29/42 ,  C30B29/52 ,  C30B33/06 ,  H01L21/76256 ,  Y10S438/933

摘要： A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.

摘要翻译： 一种半导体结构，包括第一衬底和结合到衬底的外延层。 外延层具有小于10 7 cm -2的穿透位错密度和不同于第一衬底的面内晶格常数和在其上制造外延层的第二衬底。 在另一个实施例中，提供了一种处理半导体结构的方法，包括提供第一衬底; 提供包括其上设置有外延层的第二基板的层状结构，所述外延层具有与第一基板不同的面内晶格常数和小于10 7 cm -2的穿透位错密度 >; 将第一基板结合到层状结构; 并移除第二基板。

公开(公告)号：US06713326B2

公开(公告)日：2004-03-30

申请号：US10379355

申请日：2003-03-04

申请人： Zhi-Yuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri A. Antoniadis ,  Judy L. Hoyt

发明人： Zhi-Yuan Cheng ,  Eugene A. Fitzgerald ,  Dimitri A. Antoniadis ,  Judy L. Hoyt

IPC分类号： H01L2100

CPC分类号： H01L21/76254 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02521 ,  H01L21/02532 ,  H01L21/02546 ,  Y10S438/933

摘要： A process for producing monocrystalline semiconductor layers. In an exemplary embodiment, a graded Si1−xGex (x increases from 0 to y) is deposited on a first silicon substrate, followed by deposition of a relaxed Si1−yGey layer, a thin strained Si1−zGez layer and another relaxed Si1−yGey layer. Hydrogen ions are then introduced into the strained SizGez layer. The relaxed Si1−yGey layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the strained Si layer, such that the second relaxed Si1−yGey layer remains on the second substrate. In another exemplary embodiment, a graded Si1−xGex is deposited on a first silicon substrate, where the Ge concentration x is increased from 0 to 1. Then a relaxed GaAs layer is deposited on the relaxed Ge buffer. As the lattice constant of GaAs is close to that of Ge, GaAs has high quality with limited dislocation defects. Hydrogen ions are introduced into the relaxed GaAs layer at the selected depth. The relaxed GaAs layer is bonded to a second oxidized substrate. An annealing treatment splits the bonded pair at the hydrogen ion rich layer, such that the upper portion of relaxed GaAs layer remains on the second substrate.

摘要翻译： 一种制造单晶半导体层的方法。 在示例性实施例中，分级的Si1-xGex（x从0增加到y）沉积在第一硅衬底上，随后沉积弛豫的Si1-yGey层，薄的应变Si1-zGez层和另一个弛豫的Si1-yGey 层。 然后将氢离子引入应变SizGez层。 松弛的Si1-yGey层与第二氧化基底结合。 退火处理在接合的Si层处分离结合对，使得第二弛豫Si1-yGey层保留在第二基板上。 在另一个示例性实施例中，分级的Si1-xGex沉积在第一硅衬底上，其中Ge浓度x从0增加到1.然后在弛豫的Ge缓冲器上沉积弛豫的GaAs层。 由于GaAs的晶格常数接近于Ge，所以GaAs具有高质量和有限的位错缺陷。 在所选择的深度处将氢离子引入到松弛的GaAs层中。 松弛的GaAs层结合到第二氧化衬底上。 退火处理在氢离子富集层处分离结合对，使得松弛的GaAs层的上部保留在第二基板上。

公开(公告)号：US06689211B1

公开(公告)日：2004-02-10

申请号：US09599260

申请日：2000-06-22

申请人： Kenneth C. Wu ,  Eugene A. Fitzgerald ,  Jeffrey T. Borenstein ,  Gianna Taraschi

发明人： Kenneth C. Wu ,  Eugene A. Fitzgerald ,  Jeffrey T. Borenstein ,  Gianna Taraschi

IPC分类号： C30B2522

CPC分类号： H01L21/30608 ,  H01L21/76256 ,  Y10S117/915

摘要： A SiGe monocrystalline etch-stop material system on a monocrystalline silicon substrate. The etch-stop material system can vary in exact composition, but is a doped or undoped Si1−xGex alloy with x generally between 0.2 and 0.5. Across its thickness, the etch-stop material itself is uniform in composition. The etch stop is used for micromachining by aqueous anisotropic etchants of silicon such as potassium hydroxide, sodium hydroxide, lithium hydroxide, ethylenediamine/pyrocatechol/pyrazine (EDP), TMAH, and hydrazine. These solutions generally etch any silicon containing less than 7×1019 cm−3 of boron or undoped Si1−xGex alloys with x less than approximately 18. Alloying silicon with moderate concentrations of germanium leads to excellent etch selectivities, i.e., differences in etch rate versus pure undoped silicon. This is attributed to the change in energy band structure by the addition of germanium. Furthermore, the nondegenerate doping in the Si1−xGex alloy should not affect the etch-stop behavior. The etch-stop of the invention includes the use of a graded-composition buffer between the silicon substrate and the SiGe etch-stop material. Nominally, the buffer has a linearly-changing composition with respect to thickness, from pure silicon at the substrate/buffer interface to a composition of germanium, and dopant if also present, at the buffer/etch-stop interface which can still be etched at an appreciable rate. Here, there is a strategic jump in germanium and concentration from the buffer side of the interface to the etch-stop material, such that the etch-stop layer is considerably more resistant to the etchant. This process and layer structure allows for an entire range of new materials for microelectronics. The etch-stop capabilities introduce new novel processes and structures such as relaxed SiGe alloys on Si, SiO2, and SiO2/Si. Such materials are useful for future strained Si MOSFET devices and circuits.

公开(公告)号：US06649480B2

公开(公告)日：2003-11-18

申请号：US09884172

申请日：2001-06-19

申请人： Eugene A. Fitzgerald ,  Nicole Gerrish

发明人： Eugene A. Fitzgerald ,  Nicole Gerrish

IPC分类号： H01L21336

CPC分类号： H01L27/0922 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054

摘要： A method of fabricating a CMOS inverter including providing a heterostructure having a Si substrate, a relaxed Si1-x Gex layer on the Si substrate, and a strained surface layer on said relaxed Si1-x Gex layer; and integrating a pMOSFET and an nMOSFET in said heterostructure, wherein the channel of said pMOSFET and the channel of the nMOSFET are formed in the strained surface layer. Another embodiment provides a method of fabricating an integrated circuit including providing a heterostructure having a Si substrate, a relaxed Si1-xGex layer on the Si substrate, and a strained layer on the relaxed Si1-x Gex layer; and forming a p transistor and an n transistor in the heterostructure, wherein the strained layer comprises the channel of the n transistor and the p transistor, and the n transistor and the p transistor are interconnected in a CMOS circuit.

摘要翻译： 一种制造CMOS反相器的方法，包括提供具有Si衬底的异质结构，Si衬底上的弛豫Si1-xGex层以及所述弛豫Si1-xGex层上的应变表面层; 以及将pMOSFET和nMOSFET集成在所述异质结构中，其中所述pMOSFET的沟道和nMOSFET的沟道形成在应变表面层中。 另一实施例提供一种制造集成电路的方法，包括提供具有Si衬底，Si衬底上的弛豫Si1-xGex层的异质结构和弛豫Si1-xGex层上的应变层; 以及在所述异质结构中形成p晶体管和n晶体管，其中所述应变层包括所述n晶体管和所述p晶体管的沟道，并且所述n晶体管和所述p晶体管在CMOS电路中互连。

公开(公告)号：US06646322B2

公开(公告)日：2003-11-11

申请号：US09906438

申请日：2001-07-16

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： H01L2900

CPC分类号： H01L21/02381 ,  H01L21/0245 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/76251 ,  H01L21/76256 ,  H01L21/823412 ,  H01L21/823807 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66893 ,  H01L29/66916 ,  H01L29/7838 ,  H01L29/802

摘要： Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. By allowing the MOSFET channel to be either at the surface or buried, one can create high-speed digital and/or analog circuits. The planarization before the device epitaxial layers are deposited ensures a flat surface for state-of-the-art lithography.

公开(公告)号：US06602613B1

公开(公告)日：2003-08-05

申请号：US09764182

申请日：2001-01-17

申请人： Eugene A. Fitzgerald

发明人： Eugene A. Fitzgerald

IPC分类号： B32B1500

CPC分类号： C30B25/02 ,  C30B25/18 ,  C30B29/40 ,  C30B29/42 ,  C30B29/52 ,  C30B33/06 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02546 ,  H01L21/76256 ,  Y10S428/901 ,  Y10T428/12674 ,  Y10T428/12681 ,  Y10T428/24917

摘要： A semiconductor structure including a first substrate, and an epitaxial layer bonded to the substrate. The epitaxial layer has a threading dislocation density of less than 107 cm−2 and an in-plane lattice constant that is different from that of the first substrate and a second substrate on which the epitaxial layer is fabricated. In another embodiment, there is provided a method of processing a semiconductor structure including providing a first substrate; providing a layered structure including a second substrate having an epitaxial layer provided thereon, the epitaxial layer having an in-plane lattice constant that is different from that of the first substrate and a threading dislocation density of less than 107 cm−2; bonding the first substrate to the layered structure; and removing the second substrate.

摘要翻译： 一种半导体结构，包括第一衬底和结合到衬底的外延层。 外延层具有小于107cm -2的穿透位错密度和不同于第一衬底的面内晶格常数和在其上制造外延层的第二衬底。 在另一个实施例中，提供了一种处理半导体结构的方法，包括提供第一衬底; 提供包括其上设置有外延层的第二衬底的层状结构，所述外延层具有不同于第一衬底的面内晶格常数和小于107cm -2的穿透位错密度; 将第一基板结合到层状结构; 并移除第二基板。

公开(公告)号：US06589335B2

公开(公告)日：2003-07-08

申请号：US09779915

申请日：2001-02-08

申请人： Mayank Bulsara ,  Eugene A. Fitzgerald

发明人： Mayank Bulsara ,  Eugene A. Fitzgerald

IPC分类号： C30B2522

CPC分类号： C30B25/02 ,  C30B25/20 ,  C30B29/40 ,  C30B29/42 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02546

摘要： A method of processing semiconductor materials and a corresponding semiconductor structure, including providing a virtual substrate of a GaAs epitaxial film on a Si substrate, and epitaxially growing a relaxed graded layer of InxGa1−xAs at a temperature ranging upwards from about 600° C. with a subsequent process for planarization of the InGaAs alloy.