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58 条记录 (耗时 0.027 秒)

    Memory cell configuration
    53.
    发明授权
    Memory cell configuration 有权
    内存单元配置

    公开(公告)号：US06351408B1

    公开(公告)日：2002-02-26

    申请号：US09544761

    申请日：2000-04-06

    申请人： Siegfried Schwarzl ,  Lothar Risch

    发明人： Siegfried Schwarzl ,  Lothar Risch

    IPC分类号： G11C1100

    CPC分类号： H01L27/228 ,  G11C11/15 ,  G11C11/16 ,  H01L27/222

    摘要： A memory cell configuration has word lines and bit lines running transversely with respect thereto. Memory elements with a magnetoresistive effect are respectively connected between one of the word lines and one of the bit lines. The memory elements are disposed in at least two layers one above the other.

    摘要翻译： 存储单元配置具有相对于其横向延伸的字线和位线。 具有磁阻效应的存储元件分别连接在一条字线和一条位线之间。 存储元件设置在彼此之上的至少两层中。

    Memory cell configuration and method for its production
    54.
    发明授权
    Memory cell configuration and method for its production 失效
    存储单元配置及其生产方法

    公开(公告)号：US06300652B1

    公开(公告)日：2001-10-09

    申请号：US08755456

    申请日：1996-11-22

    申请人： Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

    发明人： Lothar Risch ,  Franz Hofmann ,  Rainer Bruchhaus ,  Wolfram Wersing

    IPC分类号： H01L27108

    CPC分类号： H01L27/11502 ,  H01L27/10852 ,  H01L27/11507 ,  H01L28/55 ,  H01L28/60

    摘要： A memory cell configuration and a method for its production include stacked capacitors and use a vertical storage capacitor having a ferroelectric or paraelectric storage dielectric. In order to produce the storage capacitor, a dielectric layer for the storage dielectric is produced over the whole area. The dielectric layer is subsequently structured and first electrodes and second electrodes for the storage capacitors are formed. The invention is suitable for Gbit DRAMs and for nonvolatile memories.

    摘要翻译： 存储单元配置及其制造方法包括堆叠电容器，并且使用具有铁电或顺电存储电介质的垂直存储电容器。 为了制造存储电容器，在整个区域上产生用于存储电介质的电介质层。 随后构造电介质层，形成用于存储电容器的第一电极和第二电极。 本发明适用于Gbit DRAM和非易失性存储器。

    Method for manufacturing an integrated circuit having at least one MOS transistor
    56.
    发明授权
    Method for manufacturing an integrated circuit having at least one MOS transistor 失效
    一种具有至少一个MOS晶体管的集成电路的制造方法

    公开(公告)号：US5443992A

    公开(公告)日：1995-08-22

    申请号：US332733

    申请日：1994-11-01

    申请人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

    发明人： Lothar Risch ,  Thomas Vogelsang ,  Franz Hofmann ,  Karl Hofmann

    IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L27/08 ,  H01L27/092 ,  H01L29/78 ,  H01L29/786 ,  H01L21/265 ,  H01L21/20 ,  H01L21/302 ,  H01L21/76

    CPC分类号： H01L29/66666 ,  H01L27/092 ,  H01L29/7827 ,  H01L29/42368

    摘要： An insulating layer is grown on a principal face of a substrate that comprises a source terminal region. A first opening wherein the surface of the source terminal region is partially uncovered is provided in the insulating layer. A vertical layer sequence that comprises at least a channel region and a drain region for the MOS transistor is produced in the first opening by epitaxial growth of semiconductor material within situ doping. A second opening that is at least of a depth corresponding to the sum of the thicknesses of drain region and channel region is produced in the layer structure, a gate dielectric is applied on the surface thereof and a gate-electrode is applied on said gate dielectric.

    摘要翻译： 在包括源极端子区域的基板的主面上生长绝缘层。 在绝缘层中设置有源极端子区域的表面部分未覆盖的第一开口。 在第一开口中通过外延生长半导体材料在原位掺杂中产生至少包括MOS晶体管的沟道区和漏极区的垂直层序列。 在层结构中产生至少具有与漏极区域和沟道区域的厚度之和相对应的深度的第二开口，在其表面上施加栅极电介质，并且在所述栅极电介质上施加栅极电极 。

    Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench
    57.
    发明授权
    Process for making a contact betwen a capacitor electrode disposed in a trench and an MOS transistor source/drain region disposed outside the trench 失效
    在设置在沟槽中的电容器电极和设置在沟槽外部的MOS晶体管源极/漏极区之间进行接触的工艺

    公开(公告)号：US5432115A

    公开(公告)日：1995-07-11

    申请号：US284502

    申请日：1994-08-04

    申请人： Wolfgang Rosner ,  Franz Hofmann ,  Lothar Risch

    发明人： Wolfgang Rosner ,  Franz Hofmann ,  Lothar Risch

    IPC分类号： H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： To make a contact between a capacitor electrode (13) disposed in a trench (11) and an MOS transistor source/drain region disposed outside the trench, a shallow etching is carried out in a self-aligned manner with respect to a field-oxide region insulating the MOS transistor by producing the trench (11) in a substrate (1). After forming an Si.sub.3 N.sub.4 spacer (10) at the edge (8), laid bare during the etching, of the substrate (1) the part laid bare of the field-oxide region (2) is first removed with the aid of a mask and the trench (11) is completed in a further etching. The contact is produced after the formation of an SiO.sub.2 layer (12) at the surface of the trench (11) after removing the Si.sub.3 N.sub.4 spacer (10) and producing the capacitor electrode (13) at the edge (8), laid bare by removing the Si.sub.3 N.sub.4 spacer (10), of the substrate (1).

    摘要翻译： PCT No.PCT / DE93 / 00078 Sec。 371日期：1994年8月4日 102（e）日期1994年8月4日PCT提交1993年2月1日PCT公布。 出版物WO93 / 16490 日期：1993年8月19日。为了在布置在沟槽（11）中的电容器电极（13）和设置在沟槽外部的MOS晶体管源/漏区之间进行接触，以自对准的方式进行浅蚀刻 相对于通过在衬底（1）中产生沟槽（11）来绝缘MOS晶体管的场氧化物区域。 在蚀刻过程中在边缘（8）处形成Si3N4间隔物（10）之后，在衬底（1）上放置裸露的场氧化物区域（2）的部分首先借助掩模去除， 在另外的蚀刻中完成沟槽（11）。 在除去Si 3 N 4间隔物（10）之后在沟槽（11）的表面形成SiO 2层（12）并在边缘（8）处产生电容器电极（13），在通过去除 （1）的Si 3 N 4间隔物（10）。

    Large scale integrable memory cell with a trench capacitor wherein the trench edge is surrounded by a field oxide region
    58.
    发明授权
    Large scale integrable memory cell with a trench capacitor wherein the trench edge is surrounded by a field oxide region 失效
    具有沟槽电容器的大规模可积分存储单元，其中沟槽边缘被场氧化物区域包围

    公开(公告)号：US4905193A

    公开(公告)日：1990-02-27

    申请号：US372236

    申请日：1989-06-26

    申请人： Lothar Risch ,  Reinhard Tielert

    发明人： Lothar Risch ,  Reinhard Tielert

    IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10861 ,  H01L27/10829

    摘要： A large scale integrable memory cell including a field effect transistor lying at a bit line and further including a storage capacitor which is formed by the wall of a trench and a cooperating electrode. The active region of the storage cell which lies outside the trench is fashioned in the form of a strip. The end face forms one part of the trench edge and the remaining portion of the trench edge is surrounded by a field oxide region.

    摘要翻译： 一种大规模可积分存储单元，包括位于位线处的场效应晶体管，还包括由沟槽壁和配合电极形成的存储电容器。 位于沟槽外部的存储单元的有源区域以条带的形式形成。 端面形成沟槽边缘的一部分，并且沟槽边缘的剩余部分被场氧化物区域包围。