公开(公告)号：US20170033197A1

公开(公告)日：2017-02-02

申请号：US15181843

申请日：2016-06-14

Applicant: International Business Machines Corporation ,  GlobalFoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Kejia Wang ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/20 ,  H01L21/306 ,  H01L29/08

CPC classification number: H01L29/1033 ,  H01L21/30621 ,  H01L29/1054 ,  H01L29/20 ,  H01L29/41791 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor device includes a fin patterned in a substrate; a gate disposed over and substantially perpendicular to the fin; a pair of epitaxial contacts including a III-V material over the fin and on opposing sides of the gate; and a channel region between the pair of epitaxial contacts under the gate comprising an undoped III-V material between doped III-V materials, the doped III-V materials including a dopant in an amount in a range from about 1e18 to about 1e20 atoms/cm3 and contacting the epitaxial contacts.

Abstract translation: 半导体器件包括在衬底中图案化的鳍; 设置在所述翅片上并基本上垂直于所述翅片的门; 一对外延触点，包括在鳍的上方和栅极的相对侧上的III-V材料; 以及在栅极之间的一对外延触点之间的沟道区，其包括在掺杂III-V材料之间的未掺杂的III-V材料，掺杂的III-V材料包括量为约1e18至约1e20原子/ 并与外延触点接触。

公开(公告)号：US20160372332A1

公开(公告)日：2016-12-22

申请号：US15240554

申请日：2016-08-18

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc

Inventor： Balasubramanian Pranatharthiharan ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/285 ,  H01L29/66 ,  H01L29/45 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/08

CPC classification number: H01L21/823871 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823814 ,  H01L21/823864 ,  H01L23/5226 ,  H01L27/092 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/456 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628

Abstract: A method for fabricating a dual silicide device includes growing source and drain (S/D) regions for an N-type device, forming a protection layer over a gate structure and the S/D regions of the N-type device and growing S/D regions for a P-type device. A first dielectric layer is conformally deposited and portions removed to expose the S/D regions. Exposed S/D regions for the P-type device are silicided to form a liner. A second dielectric layer is conformally deposited. A dielectric fill is formed over the second dielectric layer. Contact holes are opened through the second dielectric layer to expose the liner for the P-type device and expose the protection layer for the N-type device. The S/D regions for the N-type device are exposed by opening the protection layer. Exposed S/D regions adjacent to the gate structure are silicided to form a liner for the N-type device. Contacts are formed.

公开(公告)号：US20160284822A1

公开(公告)日：2016-09-29

申请号：US15178853

申请日：2016-06-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/092 ,  H01L29/10 ,  H01L21/8238 ,  H01L21/311 ,  H01L21/02 ,  H01L29/08

CPC classification number: H01L29/66795 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/0228 ,  H01L21/31105 ,  H01L21/823814 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/165 ,  H01L29/785 ,  H01L29/7851

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate. At least one dielectric layer is formed adjacent an end portion of the semiconductor fins and within the space between adjacent semiconductor fins. A pair of sidewall spacers is formed adjacent outermost semiconductor fins at the end portion of the semiconductor fins. The at least one dielectric layer and end portion of the semiconductor fins between the pair of sidewall spacers are removed. Source/drain regions are formed between the pair of sidewall spacers.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片。 在半导体鳍片的端部附近和相邻的半导体鳍片之间的空间内形成至少一个电介质层。 在半导体翅片的端部处邻近最外半导体翅片形成一对侧壁间隔物。 去除该对侧壁间隔物之间​​的至少一个电介质层和半导体翅片的端部。 源极/漏极区域形成在该对侧壁间隔物之间​​。

公开(公告)号：US20160284599A1

公开(公告)日：2016-09-29

申请号：US15179620

申请日：2016-06-10

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES INC. ,  STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L21/8234 ,  H01L21/285 ,  H01L21/84

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filled with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地被金属材料填充以形成埋在衬底中的源极（或漏极）触点。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US09349863B2

公开(公告)日：2016-05-24

申请号：US13961522

申请日：2013-08-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Veeraraghavan S. Basker ,  Krishna Iyengar ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L27/12 ,  H01L29/78 ,  H01L29/66 ,  H01L29/165

CPC classification number: H01L29/66795 ,  H01L29/045 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

Abstract: After formation of a gate structure and a gate spacer, portions of an insulator layer underlying a semiconductor fin are etched to physically expose semiconductor surfaces of an underlying semiconductor material layer from underneath a source region and a drain region. Each of the extended source region and the extended drain region includes an anchored single crystalline semiconductor material portion that is in epitaxial alignment to the single crystalline semiconductor structure of the underlying semiconductor material layer and laterally applying a stress to the semiconductor fin. Because each anchored single crystalline semiconductor material portion is in epitaxial alignment with the underlying semiconductor material layer, the channel of the fin field effect transistor is effectively stressed along the lengthwise direction of the semiconductor fin.

Abstract translation: 在形成栅极结构和栅极间隔物之后，蚀刻半导体鳍片下面的绝缘体层的部分，以从源极区域和漏极区域下面物理地暴露下面的半导体材料层的半导体表面。 扩展源极区域和延伸漏极区域中的每一个包括锚定的单晶半导体材料部分，其与下面的半导体材料层的单晶半导体结构外延对准，并向半导体鳍片横向施加应力。 因为每个锚定的单晶半导体材料部分与下面的半导体材料层进行外延对准，所以鳍状场效应晶体管的沟道沿着半导体鳍片的长度方向被有效地应力。

公开(公告)号：US20150357441A1

公开(公告)日：2015-12-10

申请号：US14300506

申请日：2014-06-10

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Xiuyu Cai ,  Kejia Wang ,  Chun-Chen Yeh

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/28114 ,  H01L21/32137 ,  H01L21/32139 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/7848 ,  H01L29/785

Abstract: A method for making a semiconductor device includes forming laterally spaced-apart semiconductor fins above a substrate, and a gate overlying the semiconductor fins. The gate has a tapered outer surface. A first pair of sidewall spacers is formed adjacent the gate an exposed tapered outer surface is also defined. Portions of the gate are removed at the exposed tapered outer surface to define a recess. A second pair of sidewall spacers is formed covering the first pair of sidewall spacers and the recess. Source/drain regions are formed on the semiconductor fins.

Abstract translation: 制造半导体器件的方法包括在衬底上形成横向间隔开的半导体鳍片，以及覆盖半导体鳍片的栅极。 门具有锥形外表面。 在栅极附近形成第一对侧壁间隔物，露出的锥形外表面也被限定。 在露出的锥形外表面上去除栅极的部分以限定凹部。 形成第二对侧壁间隔件，覆盖第一对侧壁间隔件和凹部。 源极/漏极区域形成在半导体鳍片上。

公开(公告)号：US20150357425A1

公开(公告)日：2015-12-10

申请号：US14297822

申请日：2014-06-06

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai ,  William J. Taylor

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/823475 ,  H01L21/28518 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/785

Abstract: An integrated circuit transistor is formed on a substrate. A trench in the substrate is at least partially filed with a metal material to form a source (or drain) contact buried in the substrate. The substrate further includes a source (or drain) region in the substrate which is in electrical connection with the source (or drain) contact. The substrate further includes a channel region adjacent to the source (or drain) region. A gate dielectric is provided on top of the channel region and a gate electrode is provided on top of the gate dielectric. The substrate may be of the silicon on insulator (SOI) or bulk type. The buried source (or drain) contact makes electrical connection to a side of the source (or drain) region using a junction provided at a same level of the substrate as the source (or drain) and channel regions.

Abstract translation: 在基板上形成集成电路晶体管。 衬底中的沟槽至少部分地与金属材料填充以形成埋在衬底中的源极（或漏极）接触。 衬底还包括与源极（或漏极）接触电连接的衬底中的源极（或漏极）区域。 衬底还包括与源极（或漏极）区域相邻的沟道区域。 栅极电介质设置在沟道区域的顶部，栅电极设置在栅极电介质的顶部。 衬底可以是绝缘体上硅（SOI）或体积型。 埋入的源极（或漏极）接触器使用与源极（或漏极）和沟道区域在基底的相同水平处提供的接点，使得与源极（或漏极）区域的一侧电连接。

公开(公告)号：US11374111B2

公开(公告)日：2022-06-28

申请号：US16743293

申请日：2020-01-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Chun-Chen Yeh ,  Qing Liu ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/06 ,  H01L21/768 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165

Abstract: A semiconductor device that a fin structure, and a gate structure present on a channel region of the fin structure. A composite spacer is present on a sidewall of the gate structure including an upper portion having a first dielectric constant, a lower portion having a second dielectric constant that is less than the first dielectric constant, and an etch barrier layer between sidewalls of the first and second portion of the composite spacer and the gate structure. The etch barrier layer may include an alloy including at least one of silicon, boron and carbon.

公开(公告)号：US10749031B2

公开(公告)日：2020-08-18

申请号：US15273778

申请日：2016-09-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, Inc. ,  STMICROELECTRONICS, INC.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L29/08 ,  H01L29/45 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/768 ,  H01L21/285

Abstract: A large area electrical contact for use in integrated circuits features a non-planar, sloped bottom profile. The sloped bottom profile provides a larger electrical contact area, thus reducing the contact resistance, while maintaining a small contact footprint. The sloped bottom profile can be formed by recessing an underlying layer, wherein the bottom profile can be crafted to have a V-shape, U-shape, crescent shape, or other profile shape that includes at least a substantially sloped portion in the vertical direction. In one embodiment, the underlying layer is an epitaxial fin of a FinFET. A method of fabricating the low-resistance electrical contact employs a thin etch stop liner for use as a hard mask. The etch stop liner, e.g., HfO2, prevents erosion of an adjacent gate structure during the formation of the contact.

公开(公告)号：US20190096677A1

公开(公告)日：2019-03-28

申请号：US15712301

申请日：2017-09-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Hui Zang ,  Kangguo Cheng ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L21/28 ,  H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L29/417

Abstract: One illustrative method disclosed includes selectively forming sacrificial conductive source/drain cap structures on and in contact with first and second source/drain contact structures positioned on opposite sides of a gate of a transistor and removing and replacing the spaced-apart sacrificial conductive source/drain cap structures with first and second separate, laterally spaced-apart insulating source/drain cap structures that are positioned on the first and second source/drain contact structures. The method also includes forming a gate contact opening that extends through a space between the insulating source/drain cap structures and through the gate cap so as to expose a portion of the gate structure and forming a conductive gate contact structure (CB) that is conductively coupled to the gate structure.