公开(公告)号：US5376577A

公开(公告)日：1994-12-27

申请号：US268489

申请日：1994-06-30

申请人： Martin C. Roberts ,  Tyler A. Lowrey

发明人： Martin C. Roberts ,  Tyler A. Lowrey

IPC分类号： H01L29/41 ,  H01L21/265 ,  H01L21/76 ,  H01L21/768 ,  H01L21/8244 ,  H01L27/10 ,  H01L21/70

CPC分类号： H01L27/11 ,  H01L21/768 ,  H01L21/76895

摘要： The present invention is a Static Random Access Memory fabrication process for forming a buried contact, by the steps of: patterning a photoresist layer over the field silicon dioxide regions and the spaced apart areas of the substrate, thereby providing a buried contact implant window to expose a portion of at least one spaced apart area and an adjacent field silicon dioxide end portion; implanting an N-type dopant through the buried implant contact window, the implant forming a first N-type diffusion region in the exposed spaced apart area and changing the etch rate of the exposed field silicon dioxide end portion; stripping the masking layer; growing a sacrificial silicon dioxide layer, over the field silicon dioxide regions and the spaced apart areas of the supporting silicon substrate, thereby annealing the exposed field silicon dioxide end portion and returning the etch rate of the exposed field silicon dioxide end portion to substantially the same etch rate as prior to the implantation step; stripping the sacrificial silicon dioxide layer; growing a gate silicon dioxide layer over the spaced apart areas; depositing a first polysilicon layer over the gate silicon dioxide layer; patterning a buried contact window in the first polysilicon layer, thereby exposing the first N-type diffusion region and re-exposing the field silicon dioxide end portion; depositing a second polysilicon layer superjacent the first polysilicon layer and patterning whereby the first polysilicon layer forms a gate over the gate and the second polysilicon layer makes direct contact to the first N-type diffusion region; wherein the dopants from the patterned doped polysilicon forms a second N-type diffusion region within the first N-type diffusion region.

摘要翻译： 本发明是通过以下步骤形成掩埋触点的静态随机存取存储器制造工艺：在场二氧化硅区域和衬底的间隔开的区域上构图光致抗蚀剂层，从而提供掩埋接触植入窗口以暴露 至少一个间隔开的区域的一部分和相邻的场二氧化硅末端部分; 通过所述埋入式接触窗注入N型掺杂剂，所述注入在所述暴露的间隔开的区域中形成第一N型扩散区并改变所述暴露的场二氧化硅端部的蚀刻速率; 剥离掩模层; 在场二氧化硅区域和支撑硅衬底的间隔开的区域上生长牺牲二氧化硅层，从而使暴露的场二氧化硅端部部分退火并将暴露的场二氧化硅末端部分的蚀刻速率返回到基本相同 蚀刻速率在植入步骤之前; 剥离牺牲二氧化硅层; 在间隔开的区域上生长栅极二氧化硅层; 在栅极二氧化硅层上沉积第一多晶硅层; 在第一多晶硅层中构图掩埋的接触窗，从而暴露第一N型扩散区并再次暴露场二氧化硅端部; 在所述第一多晶硅层之上沉积第二多晶硅层并构图，由此所述第一多晶硅层在所述栅极上形成栅极，并且所述第二多晶硅层与所述第一N型扩散区直接接触; 其中来自图案化掺杂多晶硅的掺杂剂在第一N型扩散区内形成第二N型扩散区。

公开(公告)号：US5324681A

公开(公告)日：1994-06-28

申请号：US22807

申请日：1993-02-22

申请人： Tyler A. Lowrey ,  Kevin G. Duesman ,  Eugene H. Cloud

发明人： Tyler A. Lowrey ,  Kevin G. Duesman ,  Eugene H. Cloud

IPC分类号： H01L21/768 ,  H01L21/8242 ,  H01L23/525 ,  H01L27/118 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10852 ,  H01L21/76888 ,  H01L23/5252 ,  H01L27/118 ,  H01L2924/0002

摘要： The invention is directed to a concept to use a 3-dimensional DRAM capacitor as a one-time non-volatile programming element (programmable antifuse) to make redundancy repair and/or to select other options on a DRAM. The programmable element of the present invention provides some significant advantages, such as a lower programming voltage, which allows use of the DRAM's existing operating supply, and requiring only half of the operating voltage to test the element once programming is accomplished. The lower programming voltage allows for redundancy repair of defective DRAM cells (or selecting other options) to be made after the DRAM die is packaged including after it is installed at a customer's site.

摘要翻译： 本发明涉及使用三维DRAM电容器作为一次性非易失性编程元件（可编程反熔丝）来进行冗余修复和/或在DRAM上选择其它选项的概念。 本发明的可编程元件提供了一些显着的优点，例如较低的编程电压，其允许使用DRAM的现有操作电源，并且一旦完成编程，则仅需要一半的工作电压来测试元件。 较低的编程电压允许在DRAM裸片封装之后进行的故障DRAM单元的冗余修复（或选择其他选项），包括在安装在客户现场之后。

公开(公告)号：US4957878A

公开(公告)日：1990-09-18

申请号：US189411

申请日：1988-05-02

申请人： Tyler A. Lowrey ,  Randal W. Chance

发明人： Tyler A. Lowrey ,  Randal W. Chance

IPC分类号： H01L21/8242 ,  H01L27/105

CPC分类号： H01L27/10844 ,  H01L27/105

摘要： A dynamic randon access memory (DRAM) is formed in a series of masking steps, during which a first layer of polysilicon is anisotropically etched. After the anisotropic etch, junctions are added to the polysilicon through doping techniques. A second layer of polysilicon is then deposited and is isotropically etched. By the sequence, critical dimensions are established at preliminary mask layers and subsequent layers do not require the high degree of criticality of dimension.

摘要翻译： 在一系列掩蔽步骤中形成动态随机存取存储器（DRAM），在此期间第一层多晶硅被各向异性蚀刻。 在各向异性蚀刻之后，通过掺杂技术将结结添加到多晶硅中。 然后沉积第二层多晶硅并进行各向同性蚀刻。 按照顺序，临界尺寸在初步掩模层上建立，随后的层不需要高度的尺寸临界度。

公开(公告)号：US4924442A

公开(公告)日：1990-05-08

申请号：US252494

申请日：1988-09-30

申请人： Zhitong Chen ,  Gary M. Johnson ,  Ward D. Parkinson ,  Wen-Foo Chern ,  Tyler A. Lowrey ,  Thomas M. Trent

发明人： Zhitong Chen ,  Gary M. Johnson ,  Ward D. Parkinson ,  Wen-Foo Chern ,  Tyler A. Lowrey ,  Thomas M. Trent

IPC分类号： G11C11/4094

CPC分类号： G11C11/4094

摘要： A voltage sensing circuit is used to rapidly pull up a high potential node of a reference array to a value of a high potential source reduced by a threshold voltage (V.sub.CC -V.sub.T). During an enable cycle, the high potential node is precharged to a potential of V.sub.CC -V.sub.T, which turns on a transistor gated to the V.sub.CC potential. This pulls the high potential node as rapidly as possible to a high level in order to speed up the sensing process. A potential maintenance circuit provides sufficient current from the high potential source to maintain a desired potential at the high potential node.

摘要翻译： 电压感测电路用于将参考阵列的高电位节点快速上拉至阈值电压（VCC-VT）降低的高电位源的值。 在使能周期期间，高电位节点被预充电到VCC-VT的电位，VCC-VT导通晶体管门控VCC电位。 这将高电位节点尽可能快地拉到高电平，以加速感测过程。 潜在维护电路提供来自高电位源的足够的电流以在高电位节点处保持期望的电位。

公开(公告)号：US07589364B2

公开(公告)日：2009-09-15

申请号：US11264129

申请日：2005-11-02

申请人： Isamu Asano ,  Natsuki Sato ,  Tyler A. Lowrey ,  Guy C. Wicker ,  Wolodymyr Czubatyj ,  Stephen J. Hudgens

发明人： Isamu Asano ,  Natsuki Sato ,  Tyler A. Lowrey ,  Guy C. Wicker ,  Wolodymyr Czubatyj ,  Stephen J. Hudgens

IPC分类号： H01L31/112

CPC分类号： H01L45/06 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/148

摘要： A non-volatile memory element includes a first interlayer insulation layer 11 having a first through-hole 11a, a second interlayer insulation layer 12 having a second through-hole 12a formed on the first interlayer insulation layer 11, a bottom electrode 13 provided in the first through-hole 11, recording layer 15 containing phase change material provided in the second through-hole 12, a top electrode 16 provided on the second interlayer insulation layer 12, and a thin-film insulation layer 14 formed between the bottom electrode 13 and the recording layer 15. In accordance with this invention, the diameter D1 of a bottom electrode 13 buried in a first through-hole 11a is smaller than the diameter D2 of a second through-hole 12a, thereby decreasing the thermal capacity of the bottom electrode 13. Therefore, when a pore 14a is formed by dielectric breakdown in a thin-film insulation layer 14 and the vicinity is used as a heating region, the amount of heat escaping to the bottom electrode 13 is decreased, resulting in higher heating efficiency.

摘要翻译： 非易失性存储元件包括具有第一通孔11a的第一层间绝缘层11，形成在第一层间绝缘层11上的第二通孔12a的第二层间绝缘层12， 第一通孔11，设置在第二通孔12中的包含相变材料的记录层15，设置在第二层间绝缘层12上的顶部电极16和形成在底部电极13和 记录层15.根据本发明，埋在第一通孔11a中的底部电极13的直径D1小于第二通孔12a的直径D2，从而降低底部电极的热容量 因此，当通过薄膜绝缘层14中的电介质击穿形成孔14a并且将其附近用作加热区域时，向底部电极逸出的热量 13降低，导致更高的加热效率。

公开(公告)号：US07541607B2

公开(公告)日：2009-06-02

申请号：US11264091

申请日：2005-11-02

申请人： Isamu Asano ,  Tyler A. Lowrey

发明人： Isamu Asano ,  Tyler A. Lowrey

IPC分类号： H01L29/02

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/126 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1675

摘要： A non-volatile memory element includes a bottom electrode 12, a bit line 14 provided on the bottom electrode 12, and a recording layer 15 containing phase change material connected between the bottom electrode 12 and the bit line 14. In accordance with this invention, the bit line 14 is in contact with a growth initiation surface 15a of the recording layer 15. This structure can be obtained by forming the bit line 14 before the recording layer 15, resulting in a three-dimensional structure. This decreases the area of contact between the recording layer 15 and the bit line 14, decreasing heat dissipation to the bit line 14 without increasing the thickness of the recording layer 15. With this three-dimensional structure, moreover, there is no top electrode between the bit line 14 and the recording layer 15, keeping down the complexity of the fabrication process.

摘要翻译： 非易失性存储元件包括底部电极12，设置在底部电极12上的位线14和包含连接在底部电极12和位线14之间的相变材料的记录层15.根据本发明， 位线14与记录层15的生长起始表面15a接触。这种结构可以通过在记录层15之前形成位线14而获得，从而形成三维结构。 这降低了记录层15和位线14之间的接触面积，从而减小了对位线14的散热，而不增加记录层15的厚度。此外，通过这种三维结构，在三维结构之间不存在顶部电极 位线14和记录层15，从而降低制造工艺的复杂性。

公开(公告)号：US20080273379A1

公开(公告)日：2008-11-06

申请号：US12218122

申请日：2008-07-11

申请人： George A. Gordon ,  Ward D. Parkinson ,  John M. Peters ,  Tyler A. Lowrey ,  Stanford Ovshinsky ,  Guy C. Wicker ,  Ilya V. Karpov ,  Charles C. Kuo

发明人： George A. Gordon ,  Ward D. Parkinson ,  John M. Peters ,  Tyler A. Lowrey ,  Stanford Ovshinsky ,  Guy C. Wicker ,  Ilya V. Karpov ,  Charles C. Kuo

IPC分类号： G11C11/00 ,  H01L21/00

CPC分类号： G11C13/0004 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/144

摘要： A memory may be implemented with a stable chalcogenide glass which is defined as a generally amorphous chalcogenide material that does not change to a generally crystalline phase when exposed to 200° C. for 30 minutes or less. Different states may be programmed by changing the threshold voltage of the material. The threshold voltage may be changed with pulses of different amplitude and/or different pulse fall times. Reading may be done using a reference level between the threshold voltages of the two different states. A separate access device is generally not needed.

摘要翻译： 可以用稳定的硫属化物玻璃来实现记忆，硫化物玻璃被定义为当暴露于200℃下30分钟或更短时不改变为通常结晶相的通常为非晶态的硫族化物材料。 可以通过改变材料的阈值电压来编程不同的状态。 可以用不同幅度和/或不同脉冲下降时间的脉冲来改变阈值电压。 可以使用两种不同状态的阈值电压之间的参考电平进行读取。 通常不需要单独的访问设备。

公开(公告)号：US07282730B2

公开(公告)日：2007-10-16

申请号：US11037850

申请日：2005-01-18

申请人： Wolodymyr Czubatyj ,  Sergey Kostylev ,  Tyler A. Lowrey ,  Guy C. Wicker

发明人： Wolodymyr Czubatyj ,  Sergey Kostylev ,  Tyler A. Lowrey ,  Guy C. Wicker

IPC分类号： H01L47/00

CPC分类号： H01L45/1233 ,  H01L27/2427 ,  H01L45/00 ,  H01L45/06 ,  H01L45/1253 ,  H01L45/1293 ,  H01L45/141

摘要： A carbon containing layer may be formed between a pair of chalcogenide containing layers of a phase change memory. When the lower chalcogenide layer allows current to pass, a filament may be formed therein. The filament then localizes the electrical heating of the carbon containing layer, converting a relatively localized region to a lower conductivity region. This region then causes the localization of heating and current flow through the upper phase change material layer. In some embodiments, less phase change material may be required to change phase to form a phase change memory, reducing the current requirements of the resulting phase change memory.

摘要翻译： 含碳层可以形成在一对含硫族化物的含相变层的层之间。 当下部硫族化物层允许电流通过时，可以在其中形成细丝。 然后，细丝将含碳层的电加热定位，将相对局部化的区域转化为较低的导电性区域。 该区域然后导致加热和电流流过上相变材料层的定位。 在一些实施例中，可能需要较少的相变材料来改变相位以形成相变存储器，从而减少所得到的相变存储器的电流要求。

公开(公告)号：US07170103B2

公开(公告)日：2007-01-30

申请号：US11210357

申请日：2005-08-24

申请人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung Tri Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

发明人： Fernando Gonzalez ,  Tyler A. Lowrey ,  Trung Tri Doan ,  Raymond A. Turi ,  Graham R. Wolstenholme

IPC分类号： H01L29/88 ,  H01L29/861

CPC分类号： H01L21/02667 ,  H01L21/02532 ,  H01L21/2022 ,  H01L27/0814 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/24 ,  H01L29/6609 ,  H01L29/66136 ,  H01L29/861 ,  H01L45/04 ,  H01L45/145 ,  Y10S257/903 ,  Y10S257/91 ,  Y10S438/979

摘要： A method of making a vertical diode is provided, the vertical diode having associated therewith a diode opening extending through an insulation layer and contacting an active region on a silicon wafer. A titanium silicide layer covers the interior surface of the diode opening and contacts the active region. The diode opening is initially filled with an amorphous silicon plug that is doped during deposition and subsequently recrystallized to form large grain polysilicon. The silicon plug has a top portion that is heavily doped with a first type dopant and a bottom portion that is lightly doped with a second type dopant. The top portion is bounded by the bottom portion so as not to contact the titanium silicide layer. For one embodiment of the vertical diode, a programmable resistor contacts the top portion of the silicon plug and a metal line contacts the programmable resistor.

摘要翻译： 提供了一种制造垂直二极管的方法，该垂直二极管具有与其相连的二极管开口，其延伸穿过绝缘层并接触硅晶片上的有源区。 硅化钛层覆盖二极管开口的内表面并接触有源区。 二极管开口最初填充有非晶硅插塞，其在沉积期间被掺杂，随后再结晶以形成大晶粒多晶硅。 硅插头具有重掺杂有第一类型掺杂剂的顶部部分和轻掺杂有第二类型掺杂剂的底部部分。 顶部由底部界定，以便不与硅化钛层接触。 对于垂直二极管的一个实施例，可编程电阻器接触硅插头的顶部并且金属线接触可编程电阻器。

公开(公告)号：US06995059B2

公开(公告)日：2006-02-07

申请号：US10627468

申请日：2003-07-25

申请人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

发明人： Tyler A. Lowrey ,  Luan C. Tran ,  Alan R. Reinberg ,  Mark Durcan

IPC分类号： H01L21/8242

CPC分类号： H01L28/90 ,  H01L27/10814 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/84 ,  H01L28/91

摘要： Methods of forming capacitors, methods of forming capacitor-over-bit line memory circuitry, and related integrated circuitry constructions are described. In one embodiment, a capacitor storage node is formed having an uppermost surface and an overlying insulative material over the uppermost surface. Subsequently, a capacitor dielectric functioning region is formed discrete from the overlying insulative material operably proximate at least a portion of the capacitor storage node. A cell electrode layer is formed over the capacitor dielectric functioning region and the overlying insulative material.