公开(公告)号：US07470590B2

公开(公告)日：2008-12-30

申请号：US11455023

申请日：2006-06-15

申请人： Werner Juengling ,  Steven M. McDonald ,  Kunal R. Parekh

发明人： Werner Juengling ,  Steven M. McDonald ,  Kunal R. Parekh

IPC分类号： H01L21/336

CPC分类号： H01L23/5256 ,  H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention includes methods by which a fuse box of a semiconductor construction is fabricated to have a substantially uniform layer over fuses extending therein. In particular aspects, the invention includes methods in which one or more processing steps associated with fabrication and patterning of bond pads and redistribution layers is conducted simultaneously over a fuse box region to form and/or remove materials that are directly over the fuse box region.

摘要翻译： 本发明包括一种方法，通过该方法制造半导体结构的保险丝盒以在其中延伸的保险丝上具有基本均匀的层。 在具体方面，本发明包括这样的方法，其中与保险丝盒区域同时进行与接合焊盘和再分配层的制造和图案相关联的一个或多个处理步骤，以形成和/或去除直接在保险丝盒区域上方的材料。

公开(公告)号：US20080166856A1

公开(公告)日：2008-07-10

申请号：US12051620

申请日：2008-03-19

申请人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

发明人： Kunal R. Parekh ,  Suraj Mathew ,  Jigish D. Trivedi ,  John K. Zahurak ,  Sanh D. Tang

IPC分类号： H01L21/76

CPC分类号： H01L27/10876 ,  H01L27/10823

摘要： The invention includes methods of forming recessed access devices. A substrate is provided to have recessed access device trenches therein. A pair of the recessed access device trenches are adjacent one another. Electrically conductive material is formed within the recessed access device trenches, and source/drain regions are formed proximate the electrically conductive material. The electrically conductive material and source/drain regions together are incorporated into a pair of adjacent recessed access devices. After the recessed access device trenches are formed within the substrate, an isolation region trench is formed between the adjacent recessed access devices and filled with electrically insulative material to form a trenched isolation region.

摘要翻译： 本发明包括形成凹入进入装置的方法。 提供基板以在其中具有凹入的接入装置沟槽。 一对凹进的接入设备沟槽彼此相邻。 导电材料形成在凹进的存取装置沟槽内，源极/漏极区域靠近导电材料形成。 导电材料和源极/漏极区域一起被并入一对相邻的凹进入器件中。 在凹陷的访问设备沟槽形成在衬底内之后，在相邻的凹进的访问设备之间形成隔离区沟槽，并且填充有电绝缘材料以形成沟槽隔离区域。

公开(公告)号：US07358568B2

公开(公告)日：2008-04-15

申请号：US11305598

申请日：2005-12-16

申请人： Michael J. Hermes ,  Kunal R. Parekh

发明人： Michael J. Hermes ,  Kunal R. Parekh

IPC分类号： H01L29/76

CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/76889 ,  H01L21/823425 ,  H01L21/823475

摘要： A process for forming a semiconductor device comprises the steps of providing a semiconductor substrate assembly comprising a semiconductor wafer having an active area formed therein, a plurality of transistor gates each having a TEOS cap thereon and a pair of nitride spacers along each gate, a plurality of conductive plugs each contacting the wafer, and a BPSG layer overlying the transistor gates and contacting the active area. A portion of the BPSG layer is etched thereby exposing the TEOS caps. A portion of the BPSG layer remains on the active area after completion of the etch. Subsequently, a portion of the TEOS caps are removed to expose the transistor gates and a titanium silicide layer is formed simultaneously to contact the transistor gates and the plugs. An inventive structure resulting from the inventive process is also described.

摘要翻译： 一种用于形成半导体器件的方法包括以下步骤：提供半导体衬底组件，其包括其中形成有有效区的半导体晶片，每个具有TEOS帽的多个晶体管栅极和沿着每个栅极的一对氮化物间隔物，多个 每个接触晶片的导电插塞和覆盖晶体管栅极并接触有源区的BPSG层。 BPSG层的一部分被蚀刻，从而暴露TEOS帽。 完成蚀刻后，BPSG层的一部分保留在有源区上。 随后，去除TEOS帽的一部分以暴露晶体管栅极，同时形成钛硅化物层以接触晶体管栅极和插塞。 还描述了由本发明方法产生的创造性结构。

公开(公告)号：US07276433B2

公开(公告)日：2007-10-02

申请号：US11003275

申请日：2004-12-03

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L21/00

CPC分类号： H01L21/823468 ,  H01L21/823418 ,  H01L21/823425 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11534

摘要： The invention includes methods of forming integrated circuitry, methods of forming memory circuitry, and methods of forming field effect transistors. In one implementation, conductive metal silicide is formed on some areas of a substrate and not on others. In one implementation, conductive metal silicide is formed on a transistor source/drain region and which is spaced from an anisotropically etched sidewall spacer proximate a gate of the transistor.

摘要翻译： 本发明包括形成集成电路的方法，形成存储器电路的方法以及形成场效应晶体管的方法。 在一个实施方案中，导电金属硅化物形成在衬底的一些区域上而不是其它区域上。 在一个实施方案中，导电金属硅化物形成在晶体管源极/漏极区上，并且与靠近晶体管的栅极的各向异性蚀刻的侧壁间隔开。

公开(公告)号：US06864138B2

公开(公告)日：2005-03-08

申请号：US10310723

申请日：2002-12-04

申请人： Kunal R. Parekh ,  John K. Zahurak

发明人： Kunal R. Parekh ,  John K. Zahurak

IPC分类号： H01L21/02 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10888 ,  H01L21/76895 ,  H01L27/10811 ,  H01L27/10855 ,  H01L28/84 ,  Y10S438/964

摘要： The invention encompasses DRAM constructions, capacitor constructions, integrated circuitry, and methods of forming DRAM constructions, integrated circuitry and capacitor constructions. The invention encompasses a method of forming a capacitor wherein: a) a first layer is formed; b) a semiconductive material masking layer is formed over the first layer; c) an opening is etched through the masking layer and first layer to a node; d) a storage node layer is formed within the opening and in electrical connection with the masking layer; e) a capacitor storage node is formed from the masking layer and the storage node layer; and f) a capacitor dielectric layer and outer capacitor plate are formed operatively proximate the capacitor storage node.

摘要翻译： 本发明包括DRAM结构，电容器结构，集成电路以及形成DRAM结构，集成电路和电容器结构的方法。 本发明包括形成电容器的方法，其中：a）形成第一层; b）在第一层上形成半导体材料掩蔽层; c）通过掩模层和第一层将一个开口蚀刻到一个节点上; d）存储节点层形成在所述开口内并与所述掩蔽层电连接; e）从掩蔽层和存储节点层形成电容器存储节点; 以及f）在电容器存储节点处可操作地形成电容器介电层和外部电容器板。

公开(公告)号：US06825095B2

公开(公告)日：2004-11-30

申请号：US09955632

申请日：2001-09-18

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L2120

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06753617B2

公开(公告)日：2004-06-22

申请号：US10153527

申请日：2002-05-20

申请人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

发明人： William A. Stanton ,  Phillip G. Wald ,  Kunal R. Parekh

IPC分类号： H01L23544

CPC分类号： G03F9/7065 ,  H01L23/544 ,  H01L2223/54453 ,  H01L2924/0002 ,  Y10S438/975 ,  H01L2924/00

摘要： A method and resulting structure for reducing refraction and reflection occurring at the interface between adjacent layers of different materials in a semiconductor device, assembly or laminate during an alignment step in a semiconductor device fabrication process. The method comprises forming a planar-surfaced layer of material, having a first index of refraction, over a substrate of the semiconductor device, assembly or laminate. A corrective layer is formed over the planar-surfaced layer and a second layer, having a second index of refraction, is then formed over the corrective layer. The corrective layer is composed of a material having an intermediate index of refraction between the first index of refraction and the second index of refraction. The method can also be modified to include one or more layers of materials and/or intermediate refraction layers interposed between or above any of the aforementioned adjacent layers. The aforementioned method and resulting structures can be further modified by forming an additional layer of material, having the requisite intermediate index of refraction, over an uppermost layer to further reduce reflection occurring at the interface between the uppermost layer and air. The invention is also directed to semiconductor devices, assemblies or laminates formed through the aforementioned methods and incorporating the aforementioned structures.

摘要翻译： 一种用于在半导体器件制造工艺中的对准步骤期间在半导体器件，组件或层压体中的不同材料的相邻层之间的界面处发生折射和反射的方法和结果。 该方法包括在半导体器件，组件或层压体的衬底上形成具有第一折射率的材料的平面表面层。 在平坦表面层上形成校正层，然后在校正层上形成具有第二折射率的第二层。 校正层由在第一折射率和第二折射率之间具有中间折射率的材料组成。 该方法还可以被修改为包括插入在任何上述相邻层之间或之上的一层或多层材料和/或中间折射层。 可以通过在最上层上形成具有必要的中间折射率的附加材料层来进一步改进上述方法和所得结构，以进一步减少在最上层与空气之间的界面处发生的反射。 本发明还涉及通过上述方法形成并结合上述结构的半导体器件，组件或层压体。

公开(公告)号：US06710390B2

公开(公告)日：2004-03-23

申请号：US09261920

申请日：1999-03-03

申请人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

发明人： Kunal R. Parekh ,  John K. Zahurak ,  Phillip G. Wald

IPC分类号： H01L27108

CPC分类号： H01L27/10888 ,  H01L27/10852 ,  H01L27/10855 ,  H01L28/82 ,  H01L28/84 ,  H01L28/90 ,  H01L29/94 ,  Y10S438/964

摘要： The invention includes a number of methods and structures pertaining to semiconductor circuit technology, including: methods of forming DRAM memory cell constructions; methods of forming capacitor constructions; DRAM memory cell constructions; capacitor constructions; and monolithic integrated circuitry. The invention includes a method of forming a capacitor comprising the following steps: a) forming a mass of silicon material over a node location, the mass comprising exposed doped silicon and exposed undoped silicon; b) substantially selectively forming rugged polysilicon from the exposed undoped silicon and not from the exposed doped silicon; and c) forming a capacitor dielectric layer and a complementary capacitor plate proximate the rugged polysilicon and doped silicon. The invention also includes a capacitor comprising: a) a first capacitor plate; b) a second capacitor plate; c) a capacitor dielectric layer intermediate the first and second capacitor plates; and d) at least one of the first and second capacitor plates comprising a surface against the capacitor dielectric layer and wherein said surface comprises both doped rugged polysilicon and doped non-rugged polysilicon.

摘要翻译： 本发明包括许多与半导体电路技术有关的方法和结构，包括：形成DRAM存储单元结构的方法; 形成电容器结构的方法; DRAM存储单元结构; 电容器结构; 和单片集成电路。 本发明包括一种形成电容器的方法，包括以下步骤：a）在节点位置上形成硅材料块，所述质量包括暴露的掺杂硅和暴露的未掺杂硅; b）从暴露的未掺杂的硅而不是暴露的掺杂的硅基本上选择性地形成坚固的多晶硅; 以及c）在坚固的多晶硅和掺杂硅附近形成电容器电介质层和互补的电容器板。 本发明还包括一种电容器，包括：a）第一电容器板; b）第二电容器板; c）在第一和第二电容器板之间的电容器电介质层; 以及d）所述第一和第二电容器板中的至少一个包括抵抗所述电容器介电层的表面，并且其中所述表面包括掺杂的坚固的多晶硅和掺杂的非坚固的多晶硅。

公开(公告)号：US06599840B2

公开(公告)日：2003-07-29

申请号：US10194833

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.

公开(公告)号：US06596642B2

公开(公告)日：2003-07-22

申请号：US10193801

申请日：2002-07-11

申请人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

发明人： Zhiqiang Wu ,  Li Li ,  Thomas A. Figura ,  Kunal R. Parekh ,  Pai-Hung Pan ,  Alan R. Reinberg ,  Kin F. Ma

IPC分类号： H01L2100

CPC分类号： H01L27/10852 ,  H01L21/2815 ,  H01L21/28525 ,  H01L21/30608 ,  H01L21/32134 ,  H01L21/76232 ,  H01L21/76237 ,  H01L21/7624 ,  H01L21/76838 ,  H01L21/76897 ,  H01L27/10817 ,  H01L28/60 ,  H01L29/66492 ,  H01L29/66575

摘要： Methods are disclosed for forming shaped structures from silicon and/or germanium containing material with a material removal process that is selective to low stress portions of the material. In general, the method initially provides a layer of the material on a semiconductor substrate. The material, which has uniform stress therein, is then masked, and the stress in a portion of the material is reduced, such as by implanting ions into an unmasked portion. The mask is removed, and either the high stress masked portion or the low stress unmasked portion of the material is selectively removed, preferably by an etching process. The portion of the material not removed remains and forms a shaped structure. The various methods are used to form raised shaped structures, shaped openings, polysilicon plugs, capacitor storage nodes, surround-gate transistors, free-standing walls, interconnect lines, trench capacitors, and trench isolation regions.