公开(公告)号：US20050117393A1

公开(公告)日：2005-06-02

申请号：US11028313

申请日：2005-01-04

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/15 ,  G11C29/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08

CPC分类号： G11C11/16 ,  G11C11/15 ,  G11C29/44 ,  G11C29/785

摘要： A program element has a magnetic layer electrically connected between first and second nodes. At least a portion of the magnetic layer forms a link portion designed to be blown with external laser irradiation. The magnetic layer is provided in the same layer as and with the same structure as a tunneling magneto-resistance element in an MTJ memory cell. An electrical contact between the magnetic layer and respective one of the first and second nodes has the same structure as the electrical contact between the tunneling magneto-resistance element and an interconnection provided in the same metal interconnection layer as respective one of the first and second nodes in the MTJ memory cell.

摘要翻译： 程序元件具有电连接在第一和第二节点之间的磁性层。 磁性层的至少一部分形成设计成被外部激光照射吹制的连接部分。 磁性层设置在与MTJ存储单元中的隧道磁阻元件相同的层中，具有相同的结构。 磁性层与第一和第二节点中的相应一个之间的电接触具有与隧道磁阻元件和设置在与第一和第二节点中的相应金属互连层相同的金属互连层中的互连之间的电接触的结构相同的结构 在MTJ存储单元中。

公开(公告)号：US20050094449A1

公开(公告)日：2005-05-05

申请号：US11003504

申请日：2004-12-06

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  G11B21/02

CPC分类号： G11C11/16

摘要： A tunneling magneto-resistance element forming an MTJ memory cell has an elongated form having an aspect ratio larger than one for stabilizing the magnetization characteristics. Bit lines and write word lines for carrying data write currents are arranged along short and long sides of the tunneling magneto-resistance element, respectively. The data write current flowing through the bit line, which can easily have an interconnection width, is designed to be larger than the data write current flowing through the write word line. For example, a distance between the write word line and the tunneling magneto-resistance element is smaller than a distance between the bit line and the tunneling magneto-resistance element.

摘要翻译： 形成MTJ存储单元的隧道磁阻元件具有长宽比大于1的细长形状，用于稳定磁化特性。 用于承载数据写入电流的位线和写入字线分别沿隧道磁阻元件的短边和长边布置。 流经位线的数据写入电流（其易于具有互连宽度）被设计为大于流过写入字线的数据写入电流。 例如，写字线和隧道磁阻元件之间的距离小于位线和隧道磁阻元件之间的距离。

公开(公告)号：US06865103B2

公开(公告)日：2005-03-08

申请号：US10153737

申请日：2002-05-24

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/14 ,  G11C11/15 ,  G11C29/00 ,  G11C29/04 ,  G11C11/00

CPC分类号： G11C29/846 ,  G11C11/15

摘要： In data write operation, a data write current starts being supplied to a write word line of the selected row at a first time without waiting for redundant determination. A data write current starts being supplied to a bit line or sub bit line of the selected column at a second time that is later than the first time according to the redundant determination result. The redundant determination is conducted between the first and second times. The data write currents flowing through the write word line and the bit line generate magnetic fields of the hard-axis and easy-axis directions for the selected memory sell, respectively.

摘要翻译： 在数据写入操作中，数据写入电流开始被提供给所选行的写字线，而不等待冗余确定。 根据冗余确定结果，数据写入电流开始被提供给所选列的位线或子位线，该第二时间晚于第一次。 冗余确定在第一次和第二次之间进行。 流经写字线和位线的数据写入电流分别产生所选存储器的硬轴和易轴方向的磁场。

公开(公告)号：US06845477B2

公开(公告)日：2005-01-18

申请号：US09799581

申请日：2001-03-07

申请人： Hideto Hidaka ,  Tsukasa Ooishi

发明人： Hideto Hidaka ,  Tsukasa Ooishi

IPC分类号： G01R1/073 ,  G11C29/48 ,  H01L21/66 ,  G01R31/28 ,  G01R31/26

CPC分类号： G11C29/48

摘要： A plurality of test target chips on a test target wafer are simultaneously and electrically coupled to a plurality of chips on a test wafer via a wafer contactor. Each chip on the test wafer has a test circuit for conducting an operation test on each chip on the test target wafer. Since the test circuit is in a one-to-one relationship with respect to the test target chip, and is arranged on the test wafer other than the test target wafer, the many chips can be simultaneously tested in parallel during the wafer test without increasing an area of the test target chips.

摘要翻译： 测试目标晶片上的多个测试目标芯片通过晶片接触器同时并电耦合到测试晶片上的多个芯片。 测试晶片上的每个芯片具有用于对测试目标晶片上的每个芯片进行操作测试的测试电路。 由于测试电路相对于测试目标芯片是一对一的关系，并且被布置在除了测试目标晶片之外的测试晶片上，所以许多芯片可以在晶片测试期间并行同时测试而不增加 测试目标芯片的一个区域。

公开(公告)号：US20050007862A1

公开(公告)日：2005-01-13

申请号：US10898969

申请日：2004-07-27

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/409 ,  G11C7/06 ,  G11C7/12 ,  G11C7/18 ,  G11C11/401 ,  G11C11/407 ,  G11C7/02

CPC分类号： G11C7/06 ,  G11C7/12 ,  G11C7/18

摘要： A semiconductor device comprises a memory cell block and a sense amplifier zone. A selection gate included in the sense amplifier zone is turned on for selectively coupling the memory cell block with the sense amplifier zone. Local drivers are dispersively arranged on a BLI wire transmitting a gate control signal, and a driver is arranged on an end of the BLI wire. The driver pulls down the potential of the BLI wire at a high speed.

摘要翻译： 半导体器件包括存储器单元块和读出放大器区域。 包括在感测放大器区域中的选择栅极导通，以便将存储器单元块与读出放大器区域选择性地耦合。 本地驱动器分散布置在传输门控制信号的BLI线上，并且驱动器布置在BLI线的一端。 驾驶员以高速拉下BLI线的电位。

公开(公告)号：US20050007834A1

公开(公告)日：2005-01-13

申请号：US10885706

申请日：2004-07-08

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C11/15 ,  G11C5/00 ,  G11C11/16

CPC分类号： G11C11/16

摘要： First and second current drivers are connected to one end of corresponding first and second write bit lines, respectively, and the first and second write bit lines are directly connected, at the other end, to a common line. The first and second current drivers receive a first power supply voltage and the ground voltage, while the common line receives a second power supply voltage higher than the ground voltage and lower than the first power supply voltage. The first and second current drivers cause a current for data writing to flow in a first direction based on a voltage difference between the first power supply voltage and the second power supply voltage, and cause a current for data writing to flow in a second direction based on a voltage difference between the second power supply voltage and the ground voltage.

摘要翻译： 第一和第二电流驱动器分别连接到对应的第一和第二写位线的一端，并且第一和第二写位线在另一端直接连接到公共线。 第一和第二电流驱动器接收第一电源电压和接地电压，而公共线接收高于接地电压并低于第一电源电压的第二电源电压。 第一和第二电流驱动器使得数据写入的电流基于第一电源电压和第二电源电压之间的电压差在第一方向上流动，并且使数据写入的电流沿第二方向流动 在第二电源电压和接地电压之间的电压差。

公开(公告)号：US06791875B2

公开(公告)日：2004-09-14

申请号：US10189528

申请日：2002-07-08

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C1114

CPC分类号： G11C11/16

摘要： Two complementary bit lines corresponding to a selected column are pulled down to a ground voltage via each of a selected MTJ memory cell and a dummy memory cell and are pulled up to a power supply voltage via a read drive selection gate. A read gate corresponding to the selected column drives the voltages of two complementary read data buses by driving force according to the voltage of corresponding complementary two bit lines, respectively. A data reading circuit executes data reading operation on the basis of a voltage difference between the complementary two read data buses. The power supply voltage is determined in consideration of reliability of a tunneling insulating film of an MTJ memory cell.

摘要翻译： 对应于所选列的两个互补位线通过所选择的MTJ存储器单元和虚设存储单元中的每一个被下拉至接地电压，并经由读驱动选择门被上拉至电源电压。 对应于所选择的列的读取门分别根据对应的互补的两个位线的电压通过驱动力来驱动两个互补读数据总线的电压。 数据读取电路基于互补的两条读取数据总线之间的电压差来执行数据读取操作。 考虑到MTJ存储单元的隧道绝缘膜的可靠性来确定电源电压。

公开(公告)号：US06778430B2

公开(公告)日：2004-08-17

申请号：US09887321

申请日：2001-06-25

申请人： Hideto Hidaka

发明人： Hideto Hidaka

IPC分类号： G11C1114

CPC分类号： H01L27/228 ,  G11C8/08 ,  G11C11/15 ,  G11C11/16

摘要： An MTJ memory cell is independently provided with a write word line and a read word line used for data write and data read. By separately arranging read word lines every two regions formed by dividing a memory array in the column direction, it is possible to reduce signal propagation delays of the read word lines and accelerate the data read operation. Activation of each read word line is controlled by a write word line in accordance with a row selection result in a hierarchical manner. A word-line-current control circuit forms and cuts off the current path of a write word line correspondingly to data write and data read.

摘要翻译： MTJ存储单元独立地具有用于数据写入和数据读取的写字线和读字线。 通过在列方向上划分存储器阵列形成的每两个区域分开布置读取字线，可以减少读取字线的信号传播延迟并加速数据读取操作。 每个读取字线的激活根据分层方式的行选择结果由写入字线控制。 字线电流控制电路对应于数据写入和数据读取形成并切断写入字线的当前路径。

公开(公告)号：US06777986B2

公开(公告)日：2004-08-17

申请号：US10217391

申请日：2002-08-14

申请人： Hideto Hidaka ,  Masakazu Hirose

发明人： Hideto Hidaka ,  Masakazu Hirose

IPC分类号： H03K300

CPC分类号： H03K19/00361

摘要： A data output drive transistor is rendered conductive when the potential of an internal node attains an H level, whereby an output node is discharged to the level of ground potential. When the drive transistor is turned on, the output node is discharged to the level of ground potential at high speed. This drive transistor is turned on for a predetermined time period when output of a high level data is completed, whereby the output node is discharged to the level of the ground potential for a predetermined time period. As a result, the potential of the output node is lowered from a high level to an intermediate level, so that the amplitude of a subsequent output signal is reduced. An output circuit that can effectively prevent generation of ringing with no increase in the access time is provided. A countermeasure is provided to suppress a ringing at output node which drives the output node at high speed when the output node potential attains a potential at which no ringing is caused. A stable output signal is provided at high speed.

摘要翻译： 当内部节点的电位达到H电平时，数据输出驱动晶体管导通，从而将输出节点放电到地电位。 当驱动晶体管导通时，输出节点以高速放电到地电位。 当高电平数据的输出完成时，该驱动晶体管导通预定时间段，由此输出节点在预定时间段内被放电到地电位的电平。 结果，输出节点的电位从高电平降低到中间电平，使得后续输出信号的幅度减小。 提供了可以有效地防止产生振铃而不增加访问时间的输出电路。 提供了一种对策，用于当输出节点电位达到不产生振铃的电位时，抑制在输出节点处高速驱动输出节点的振铃。 高速提供稳定的输出信号。

公开(公告)号：US06621306B2

公开(公告)日：2003-09-16

申请号：US10036406

申请日：2002-01-07

申请人： Tsukasa Ooishi ,  Hideto Hidaka

发明人： Tsukasa Ooishi ,  Hideto Hidaka

IPC分类号： H03K19094

CPC分类号： H03K3/35625 ,  H03K3/012 ,  H03K3/356121

摘要： A random logic circuit comprises an input portion for inputting data; a first latch portion for receiving the data outputted from the input portion, and holding and outputting the data; a second latch portion for receiving the data outputted from the first latch portion, and holding and outputting the data; an output portion for receiving the data outputted from the second latch portion and outputting the data to a logic circuit; and a prevention circuit for preventing generation of a sub-threshold leak current in sleep mode between the first latch portion and the second latch portion.