公开(公告)号：US20070128840A1

公开(公告)日：2007-06-07

申请号：US10597066

申请日：2004-01-16

申请人： Huajie Chen ,  Stephen Bedell ,  Devendra Sadana ,  Dan Mocuta

发明人： Huajie Chen ,  Stephen Bedell ,  Devendra Sadana ,  Dan Mocuta

IPC分类号： H01L21/20

CPC分类号： H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

摘要： A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.

摘要翻译： 一种形成绝缘体上硅锗（SGOI）结构的方法。 SiGe层沉积在SOI晶片上。 进行SiGe和Si层的热混合以形成具有高松弛和低堆垛层错缺陷密度的厚SGOI。 然后将SiGe层变薄至所需的最终厚度。 稀释过程，Ge浓度，松弛量和堆垛层错缺陷密度均不变。 因此获得了具有高松弛和低堆垛层错缺陷密度的薄SGOI膜。 然后在薄SGOI晶片上沉积一层Si。 稀释方法包括低温​​（550℃-700℃）HIPOX或蒸汽氧化，在外延室中进行原位HCl蚀刻或CMP。 由HIPOX或蒸汽氧化稀化产生的粗糙SiGe表面在应变Si沉积期间用接触式CMP，原位氢气烘烤和SiGe缓冲层进行平滑，或者在氢气环境中用HCl，DCS混合气体加热晶片 和GeH 4。

公开(公告)号：US20070105350A1

公开(公告)日：2007-05-10

申请号：US11619040

申请日：2007-01-02

申请人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

发明人： Stephen Bedell ,  Huajie Chen ,  Anthony Domenicucci ,  Keith Fogel ,  Devendra Sadana

IPC分类号： C30B1/00 ,  H01L21/20

CPC分类号： H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

摘要： A method of fabricating high-quality, substantially relaxed SiGe-on-insulator substrate materials which may be used as a template for strained Si is described. A silicon-on-insulator substrate with a very thin top Si layer is used as a template for compressively strained SiGe growth. Upon relaxation of the SiGe layer at a sufficient temperature, the nature of the dislocation motion is such that the strain-relieving defects move downward into the thin Si layer when the buried oxide behaves semi-viscously. The thin Si layer is consumed by oxidation of the buried oxide/thin Si interface. This can be accomplished by using internal oxidation at high temperatures. In this way the role of the original thin Si layer is to act as a sacrificial defect sink during relaxation of the SiGe alloy that can later be consumed using internal oxidation.

摘要翻译： 描述了可以用作应变Si的模板的制造高质量，基本上松弛的绝缘体上硅衬底材料的方法。 使用具有非常薄的顶部Si层的绝缘体上硅衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下弛豫时，位错运动的性质使得当埋入的氧化物半粘着时，应变消除缺陷向下移动到薄的Si层中。 薄Si层被掩埋氧化物/薄Si界面的氧化所消耗。 这可以通过在高温下使用内部氧化来实现。 以这种方式，原始薄Si层的作用是在SiGe合金的弛豫期间用作牺牲缺陷陷阱，SiGe合金随后可以使用内部氧化来消耗。

公开(公告)号：US20060151787A1

公开(公告)日：2006-07-13

申请号：US10905595

申请日：2005-01-12

申请人： Huajie Chen ,  Anda Mocuta ,  Stephen Bedell ,  Effendi Leobandung ,  Devendra Sadana

发明人： Huajie Chen ,  Anda Mocuta ,  Stephen Bedell ,  Effendi Leobandung ,  Devendra Sadana

IPC分类号： H01L29/12 ,  H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532

摘要： A method and structure for fabricating a strained semiconductor on a relaxed SiGe substrate which has dopant diffusion control and defect reduction are provided. Specifically, the dopant diffusion control and defect reduction is achieved in the present invention by providing a SiGe buffer layer between the strained semiconductor and the underlying relaxed SiGe substrate. In accordance with the present invention, the SiGe buffer layer has a Ge content that is less than the Ge content which is present in the relaxed SiGe substrate.

摘要翻译： 提供了在具有掺杂剂扩散控制和缺陷减少的松弛SiGe衬底上制造应变半导体的方法和结构。 具体地，通过在应变半导体和下面的弛豫SiGe衬底之间提供SiGe缓冲层，在本发明中实现了掺杂剂扩散控制和缺陷减少。 根据本发明，SiGe缓冲层的Ge含量小于弛豫SiGe衬底中存在的Ge含量。

公开(公告)号：US20060076627A1

公开(公告)日：2006-04-13

申请号：US10711899

申请日：2004-10-12

申请人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

发明人： Huajie Chen ,  Omer Dokumaci ,  Oleg Gluschenkov ,  Werner Rausch

IPC分类号： H01L29/94

CPC分类号： H01L21/26533 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/31654 ,  H01L21/31675 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/66636

摘要： A method of forming a field effect transistor creates shallower and sharper junctions, while maximizing dopant activation in processes that are consistent with current manufacturing techniques. More specifically, the invention increases the oxygen content of the top surface of a silicon substrate. The top surface of the silicon substrate is preferably cleaned before increasing the oxygen content of the top surface of the silicon substrate. The oxygen content of the top surface of the silicon substrate is higher than other portions of the silicon substrate, but below an amount that would prevent epitaxial growth. This allows the invention to epitaxially grow a silicon layer on the top surface of the silicon substrate. Further, the increased oxygen content substantially limits dopants within the epitaxial silicon layer from moving into the silicon substrate.

摘要翻译： 形成场效应晶体管的方法产生更浅和更尖的结，同时在与当前制造技术一致的工艺中最大化掺杂剂活化。 更具体地，本发明增加了硅衬底的顶表面的氧含量。 优选在增加硅衬底的顶表面的氧含量之前清洁硅衬底的顶表面。 硅衬底的顶表面的氧含量高于硅衬底的其它部分，但低于防止外延生长的量。 这允许本发明在硅​​衬底的顶表面上外延生长硅层。 此外，增加的氧含量基本上限制外延硅层内的掺杂剂移动到硅衬底中。

公开(公告)号：US20060065914A1

公开(公告)日：2006-03-30

申请号：US10711637

申请日：2004-09-29

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Sang-Hyun Oh ,  Siddhartha Panda ,  Werner Rausch ,  Tsutomu Sato ,  Henry Utomo

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28079 ,  H01L21/7624 ,  H01L29/1045 ,  H01L29/165 ,  H01L29/4933 ,  H01L29/495 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

摘要： A field effect transistor (“FET”) is provided which includes a gate stack overlying a single-crystal semiconductor region of a substrate, a pair of first spacers disposed over sidewalls of said gate stack, and a pair of regions consisting essentially of a single-crystal semiconductor alloy which are disposed on opposite sides of the gate stack. Each of the semiconductor alloy regions is spaced a first distance from the gate stack. The source region and drain region of the FET are at least partly disposed in respective ones of the semiconductor alloy regions, such that the source region and the drain region are each spaced a second distance from the gate stack by a first spacer of the pair of first spacers, the second distance being different from the first distance.

公开(公告)号：US20060057859A1

公开(公告)日：2006-03-16

申请号：US10943048

申请日：2004-09-16

申请人： Huajie Chen

发明人： Huajie Chen

IPC分类号： H01L21/31

CPC分类号： H01L29/0847 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/66628 ,  H01L29/7834 ,  H01L29/7848

摘要： Methods for preparing a surface for selective silicon-germanium epitaxy by forming a thin silicon (Si) buffer layer or a thin, low concentration SiGe buffer layer for uniform nucleation, are disclosed.

摘要翻译： 公开了通过形成用于均匀成核的薄硅（Si）缓冲层或薄的低浓度SiGe缓冲层来制备用于选择性硅 - 锗外延的表面的方法。

公开(公告)号：US20050189589A1

公开(公告)日：2005-09-01

申请号：US10708378

申请日：2004-02-27

申请人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

发明人： Huilong Zhu ,  Philip Oldiges ,  Bruce Doris ,  Xinlin Wang ,  Oleg Gluschenkov ,  Huajie Chen ,  Ying Zhang

IPC分类号： H01L27/01 ,  H01L29/06 ,  H01L29/10 ,  H01L29/786

CPC分类号： H01L29/7849 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/7842 ,  H01L29/78603 ,  H01L29/78612 ,  H01L29/78618 ,  H01L29/78687

摘要： Channel depth in a field effect transistor is limited by an intra-layer structure including a discontinuous film or layer formed within a layer or substrate of semiconductor material. Channel depth can thus be controlled much in the manner of SOI or UT-SOI technology but with less expensive substrates and greater flexibility of channel depth control while avoiding floating body effects characteristic of SOI technology. The profile or cross-sectional shape of the discontinuous film may be controlled to an ogee or staircase shape to improve short channel effects and reduce source/drain and extension resistance without increase of capacitance. Materials for the discontinuous film may also be chosen to impose stress on the transistor channel from within the substrate or layer and provide increased levels of such stress to increase carrier mobility. Carrier mobility may be increased in combination with other meritorious effects.

摘要翻译： 场效应晶体管中的沟道深度由包括在半导体材料的层或衬底内形成的不连续膜或层的层内结构限制。 因此，可以以SOI或UT-SOI技术的方式控制通道深度，但是具有较便宜的衬底和更大的通道深度控制的灵活性，同时避免SOI技术的浮体效应特性。 不连续膜的轮廓或横截面形状可以被控制为奥格或阶梯形状，以改善短通道效应，并且在不增加电容的情况下降低源极/漏极和延伸电阻。 也可以选择用于不连续膜的材料以在衬底或层内从晶体管沟道施加应力，并提供增加的这种应力水平以增加载流子迁移率。 携带者的流动性可能会与其他有利的影响相结合。

公开(公告)号：US06906360B2

公开(公告)日：2005-06-14

申请号：US10605134

申请日：2003-09-10

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer O. Dokumaci ,  Haining S. Yang

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer O. Dokumaci ,  Haining S. Yang

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/73

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7848

摘要： A structure and method are provided in which an n-type field effect transistor (NFET) and a p-type field effect transistor (PFET) each have a channel region disposed in a single-crystal layer of a first semiconductor and a stress is applied at a first magnitude to a channel region of the PFET but not at that magnitude to the channel region of the NFET. The stress is applied by a layer of a second semiconductor which is lattice-mismatched to the first semiconductor. The layer of second semiconductor is formed over the source and drain regions and extensions of the PFET at a first distance from the channel region of the PFET and is formed over the source and drain regions of the NFET at a second, greater distance from the channel region of the NFET, or not formed at all in the NFET.

摘要翻译： 提供了一种结构和方法，其中n型场效应晶体管（NFET）和p型场效应晶体管（PFET）各自具有设置在第一半导体的单晶层中的沟道区域并施加应力 在第一幅度上与PFET的沟道区不同，但与NFET的沟道区不同。 应力由第一半导体晶格失配的第二半导体层施加。 第二半导体层形成在PFET的源极和漏极区域以及与PFET的沟道区第一距离处的延伸部分之间，并且形成在NFET的源极和漏极区域之上，距离沟道的第二更远的距离 NFET的区域，或者根本不形成在NFET中。

公开(公告)号：US06893936B1

公开(公告)日：2005-05-17

申请号：US10710255

申请日：2004-06-29

申请人： Huajie Chen ,  Stephen W. Bedell

发明人： Huajie Chen ,  Stephen W. Bedell

IPC分类号： H01L21/762 ,  H01L21/76

CPC分类号： H01L21/76254 ,  Y10S438/91

摘要： A method is disclosed for forming a semiconductor wafer having a strained Si or SiGe layer on an insulator layer. The method produces a structure having a SiGe buffer layer between the insulator layer and the strained Si or SiGe layer, but eliminates the need for Si epitaxy after bonding. The method also eliminates interfacial contamination between strained Si and SiGe buffer layer, and allows the formation of Si/SiGe layers having a total thickness exceeding the critical thickness of the strained Si layer.

摘要翻译： 公开了一种在绝缘体层上形成具有应变Si或SiGe层的半导体晶片的方法。 该方法产生在绝缘体层和应变Si或SiGe层之间具有SiGe缓冲层的结构，但是在结合之后不需要Si外延。 该方法还消除了应变Si和SiGe缓冲层之间的界面污染，并且允许形成总厚度超过应变Si层的临界厚度的Si / SiGe层。

公开(公告)号：US20050082616A1

公开(公告)日：2005-04-21

申请号：US10689506

申请日：2003-10-20

申请人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer Dokumaci

发明人： Huajie Chen ,  Dureseti Chidambarrao ,  Omer Dokumaci

IPC分类号： H01L20060101 ,  H01L21/336 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/01 ,  H01L27/12 ,  H01L29/10

CPC分类号： H01L29/7848 ,  H01L21/3081 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/092 ,  H01L29/1054 ,  H01L29/66628 ,  H01L29/66636 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

摘要翻译： 半导体器件及半导体器件的制造方法。 半导体器件包括用于pFET和nFET的沟道。 在pFET沟道的源极和漏极区域选择性地生长SiGe层，并且在nFET沟道的源极和漏极区域选择性地生长Si：C层。 SiGe和Si：C层与下层Si层的晶格网络匹配以产生应力分量。 在一个实现中，这导致pFET沟道中的压缩分量和nFET沟道中的拉伸分量。