公开(公告)号：US20240258296A1

公开(公告)日：2024-08-01

申请号：US18630302

申请日：2024-04-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Shawna M. Liff ,  Zhiguo Qian ,  Johanna M. Swan

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/532 ,  H01L23/538 ,  H01L23/66

CPC classification number: H01L25/18 ,  H01L23/5329 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/66 ,  H01L24/17 ,  H01L2223/6627 ,  H01L2224/0237

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a package substrate having a surface; a first die, having opposing first and second surfaces, in a first dielectric layer, wherein the first dielectric layer is between a second dielectric layer and the surface of the package substrate, and the first surface of the first die is coupled to the surface of the package substrate; a second die, having opposing first and second surfaces, in the second dielectric layer, and wherein the second dielectric layer is between the first dielectric layer and a third dielectric layer; a third die, having opposing first and second surfaces, in the third dielectric layer, wherein the first surface of the third die is coupled to the surface of the package substrate by a conductive pillar; and a conductive, radio frequency shield structure surrounding the conductive pillar.

公开(公告)号：US20240063132A1

公开(公告)日：2024-02-22

申请号：US17820993

申请日：2022-08-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Scott E. Siers ,  Gerald S. Pasdast ,  Johanna M. Swan ,  Henning Braunisch ,  Kimin Jun ,  Jiraporn Seangatith ,  Shawna M. Liff ,  Mohammad Enamul Kabir ,  Sathya Narasimman Tiagaraj

IPC: H01L23/538 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/5386 ,  H01L24/08 ,  H01L24/16 ,  H01L24/80 ,  H01L24/05 ,  H01L25/0652 ,  H01L25/0657 ,  H01L23/5383 ,  H01L2224/05647 ,  H01L2224/05687 ,  H01L2224/16225 ,  H01L2224/08145 ,  H01L2224/08121 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2924/37001 ,  H01L2924/3841 ,  H01L2924/3512

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of IC dies, adjacent layers in the plurality of layers being coupled together by first interconnects and a package substrate coupled to the plurality of layers by second interconnects. A first layer in the plurality of layers comprises a dielectric material surrounding a first IC die in the first layer, a second layer in the plurality of layers is adjacent and non-coplanar with the first layer, the second layer comprises a first circuit region and a second circuit region separated by a third circuit region, the first circuit region and the second circuit region are bounded by respective guard rings, and the first IC die comprises conductive pathways conductively coupling conductive traces in the first circuit region with conductive traces in the second circuit region.

公开(公告)号：US11749642B2

公开(公告)日：2023-09-05

申请号：US17706156

申请日：2022-03-28

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Amr Elshazly ,  Arun Chandrasekhar ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0652 ,  H01L23/49822 ,  H01L25/50

Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a package substrate, a first die coupled to the package substrate with first interconnects, and a second die coupled to the first die with second interconnects, wherein the second die is coupled to the package substrate with third interconnects, a communication network is at least partially included in the first die and at least partially included in the second die, and the communication network includes a communication pathway between the first die and the second die.

公开(公告)号：US20230187407A1

公开(公告)日：2023-06-15

申请号：US17548304

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Carleton L. Molnar ,  Adel A. Elsherbini ,  Tanay Karnik ,  Shawna M. Liff ,  Robert J. Munoz ,  Julien Sebot ,  Johanna M. Swan ,  Nevine Nassif ,  Gerald S. Pasdast ,  Krishna Bharath ,  Neelam Chandwani ,  Dmitri E. Nikonov

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/00

CPC classification number: H01L25/0652 ,  H01L23/481 ,  H01L24/08 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/08147 ,  H01L2924/37001 ,  H01L2924/1427

Abstract: A microelectronic assembly is provided comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer between the first layer and a third layer; and a third plurality of IC dies in the third layer. In some embodiments, the second plurality of IC dies comprises IC dies in an array of rows and columns, each IC die of the second plurality of IC dies is coupled to more than one IC die of the first plurality of IC dies, and the third plurality of IC dies is to provide electrical coupling between adjacent ones of the second plurality of IC dies.

公开(公告)号：US20230187362A1

公开(公告)日：2023-06-15

申请号：US17548078

申请日：2021-12-10

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Brandon M. Rawlings ,  Shawna M. Liff ,  Bradley A. Jackson ,  Robert J. Munoz ,  Johanna M. Swan

IPC: H01L23/538 ,  H01L25/065 ,  H01L23/498 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/5383 ,  H01L25/0652 ,  H01L23/49894 ,  H01L25/50 ,  H01L24/96

Abstract: A microelectronic assembly is provided, comprising: a first plurality of integrated circuit (IC) dies in a first layer; a second plurality of IC dies in a second layer; and a third plurality of IC dies in a third layer, in which: the second layer is between the first layer and the third layer, an interface between two adjacent layers comprises interconnects having a pitch of less than 10 micrometers between adjacent ones of the interconnects, and each of the first layer, the second layer, and the third layer comprises a dielectric material, and further comprises conductive traces in the dielectric material.

公开(公告)号：US20230170327A1

公开(公告)日：2023-06-01

申请号：US17538603

申请日：2021-11-30

Applicant: Intel Corporation

Inventor： Jin Yang ,  David Shia ,  Adel A. Elsherbini ,  Christopher M. Pelto ,  Kimin Jun ,  Bradley A. Jackson ,  Robert J. Munoz ,  Shawna M. Liff ,  Johanna M. Swan

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L25/0652 ,  H01L2225/06517 ,  H01L24/08

Abstract: A microelectronic assembly is provided, comprising: a first IC die coupled to a surface with first interconnects having a first pitch; and a second IC die coupled to the surface with second interconnects having a second pitch. The second pitch is greater than the first pitch, and the first pitch is less than 10 micrometers. In another embodiment, a microelectronic assembly is provided, comprising: a first stack coupled to a surface, the first stack comprising a first number of IC dies; and a second stack coupled to the surface, the second stack comprising a second number of IC dies, in which: the first stack and the second stack are laterally surrounded by a dielectric, the first stack and the second stack have a same thickness, and the first number is less than the second number.

公开(公告)号：US20230163098A1

公开(公告)日：2023-05-25

申请号：US17531374

申请日：2021-11-19

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  William J. Lambert ,  Krishna Bharath ,  Shawna M. Liff ,  Nicolas Butzen ,  Georgios Dogiamis ,  Gerald S. Pasdast ,  Vivek Kumar Rajan ,  Sathya Narasimman Tiagaraj ,  Timothy Francis Schmidt

IPC: H01L25/065

CPC classification number: H01L25/0652 ,  H01L25/18

Abstract: Embodiments of the present disclosure provide a microelectronic assembly comprising: an integrated circuit (IC) die in a first layer and a plurality of IC dies in a second layer, at least two adjacent IC dies in the plurality being electrically coupled along their proximate edges by the IC die. The first layer and the second layer are electrically and mechanically coupled by interconnects having a pitch of less than 10 micrometers between adjacent interconnects, and the IC die comprises capacitors and voltage regulator circuitry.

公开(公告)号：US11605603B2

公开(公告)日：2023-03-14

申请号：US16397718

申请日：2019-04-29

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Georgios Dogiamis ,  Telesphor Kamgaing ,  Henning Braunisch ,  Johanna M. Swan ,  Shawna M. Liff ,  Aleksandar Aleksov

IPC: H01L27/146 ,  H01L23/00 ,  H01L23/66

Abstract: Embodiments may relate to a microelectronic package that includes a radio frequency (RF) chip coupled with a die by interconnects with a first pitch. The RF chip may further be coupled with a waveguide of a package substrate by interconnects with a second pitch that is different than the first pitch. The RF chip may facilitate conveyance of data to the waveguide as an electromagnetic signal with a frequency greater than approximately 20 gigahertz (GHz). Other embodiments may be described or claimed.

公开(公告)号：US20230074970A1

公开(公告)日：2023-03-09

申请号：US18053869

申请日：2022-11-09

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Veronica Aleman Strong ,  Shawna M. Liff ,  Brandon M. Rawlings ,  Jagat Shakya ,  Johanna M. Swan ,  David M. Craig ,  Jeremy Alan Streifer ,  Brennen Karl Mueller

IPC: H01L23/00 ,  B81B7/00

Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component having a first direct bonding region, wherein the first direct bonding region includes first metal contacts and a first dielectric material between adjacent ones of the first metal contacts; a second microelectronic component having a second direct bonding region, wherein the second direct bonding region includes second metal contacts and a second dielectric material between adjacent ones of the second metal contacts, wherein the first microelectronic component is coupled to the second microelectronic component by interconnects, and wherein the interconnects include individual first metal contacts coupled to respective individual second metal contacts; and a void between an individual first metal contact that is not coupled to a respective individual second metal contact, wherein the void is in the first direct bonding region.

公开(公告)号：US11581282B2

公开(公告)日：2023-02-14

申请号：US16117353

申请日：2018-08-30

Applicant: Intel Corporation

Inventor： Adel A. Elsherbini ,  Johanna M. Swan ,  Shawna M. Liff ,  Gerald S. Pasdast

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/56 ,  H03M9/00 ,  H01L25/065 ,  H01L25/00

Abstract: In embodiments, a semiconductor package may include a first die and a second die. The package may additionally include a serializer/deserializer (SerDes) die coupled with the first and the second dies. The SerDes die may be configured to serialize signals transmitted from the first die to the second die, and deserialize signals received from the second die. Other embodiments may be described and/or claimed.