公开(公告)号：US09910814B2

公开(公告)日：2018-03-06

申请号：US14658026

申请日：2015-03-13

Applicant: Intel Corporation

Inventor： Bryan L. Spry ,  Su Wei Lim ,  Mikal C. Hunsaker ,  Rohit R. Verma ,  Lily P. Looi ,  Ronald W. Swartz ,  Michael W. Leddige ,  Vui Yong Liew

IPC: G06F13/40 ,  G06F13/42 ,  G06F13/12

CPC classification number: G06F13/4221 ,  G06F13/122 ,  G06F13/4022 ,  G06F13/4265 ,  Y02D10/14 ,  Y02D10/151

Abstract: Techniques and mechanisms for exchanging single-ended communications with a protocol stack of an integrated circuit package. In an embodiment, an integrated circuit (IC) chip includes a protocol stack comprising a transaction layer which performs operations compatible with a Peripheral Component Interconnect Express™ (PCIe™) specification. Transaction layer packets, exchanged between the transaction layer and a link layer of the protocol stack, are compatible with a PCIe™ format. In another embodiment, a physical layer of the protocol stack is to couple the IC chip to another IC chip for an exchange of the transaction layer packets via single-ended communications. A packaged device includes both of the IC chips.

公开(公告)号：US20170132171A1

公开(公告)日：2017-05-11

申请号：US15414210

申请日：2017-01-24

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/42 ,  G06F1/06

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

公开(公告)号：US09575552B2

公开(公告)日：2017-02-21

申请号：US14129545

申请日：2013-04-17

Applicant: INTEL CORPORATION

Inventor： Choon Gun Por ,  Su Wei Lim

IPC: G06F13/36 ,  G06F1/32 ,  G06F1/26 ,  G06F13/364 ,  G06F13/42 ,  G06F13/38

CPC classification number: G06F1/3296 ,  G06F1/266 ,  G06F13/364 ,  G06F13/4221 ,  Y02D10/14 ,  Y02D10/151

Abstract: Translation circuitry for facilitating communication between a protocol stack for a PCIe™ communication protocol and a PHY layer for a low power communication standard. In an embodiment, the translation circuitry includes logic is to variously convert signaling between two or more PHY interface standards. The one or more a PHY interface standards may include a PHY Interface for PCI Express (PIPE) specification and a standard for a comparatively low power communication protocol. In another embodiment, the low power communication standard is a Reference M-PHY Module Interface (RMMI) specification.

Abstract translation: 用于促进用于PCIe TM通信协议的协议栈与用于低功率通信标准的PHY层之间的通信的翻译电路。 在一个实施例中，翻译电路包括逻辑是在两个或多个PHY接口标准之间不同地转换信令。 一个或多个PHY接口标准可以包括用于PCI Express（PIPE）规范的PHY接口和用于相对低功率通信协议的标准。 在另一个实施例中，低功率通信标准是参考M-PHY模块接口（RMMI）规范。

公开(公告)号：US09563256B2

公开(公告)日：2017-02-07

申请号：US13734577

申请日：2013-01-04

Applicant: Intel Corporation

Inventor： Sun Zheng E ,  Ting Lok Song ,  Poh Thiam Teoh ,  Jennifer Chin ,  Say Cheong Gan ,  Sujea Lim ,  Su Wei Lim

IPC: G06F1/32

CPC classification number: G06F1/3253 ,  Y02D10/151 ,  Y02D50/20

Abstract: Particular embodiments described herein can offer a method that includes powering down a root port; initiating a first downstream cycle by a central processing unit (CPU) to the root port; identifying a power up activity for the CPU; and triggering an exit flow for a power state in conjunction with sending a second downstream cycle to the root port. In more particular embodiments, the triggering of the exit flow for the power state and the sending of the second downstream cycle to the root port occurs in a substantially parallel fashion. In addition, a prewake indicator can be sent to the root port to trigger the exit flow before the CPU is powered up and the second downstream cycle is sent.

Abstract translation: 本文描述的特定实施例可以提供一种方法，其包括断电根端口; 通过中央处理单元（CPU）向根端口发起第一下游循环; 识别CPU的加电活动; 并且触发用于电力状态的退出流，同时向根端口发送第二下游循环。 在更具体的实施例中，用于功率状态的出口流的触发和将第二下游循环发送到根端口以基本上平行的方式发生。 另外，在CPU上电并发送第二个下游周期之前，可以将根据端口发送预取指示符以触发退出流。

公开(公告)号：US09418030B2

公开(公告)日：2016-08-16

申请号：US14668114

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/00 ,  G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F13/42 ,  G06F11/07 ,  G06F11/10 ,  G06F11/22 ,  G06F13/12 ,  G06F13/40 ,  G06F11/30 ,  G06F13/16

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

Abstract translation: 具有组件间通信能力的分量设备和具有这种组件设备的系统在此被公开。 在实施例中，这样的组件可以包括多个控制引脚，包括时钟引脚，多个数据引脚和逻辑单元。 逻辑单元可以被配置为通过时钟引脚从另一个组件接收时钟信号，以通过所选择的一个控制和数据引脚向另一个组件提供警报信号，以启动与其他组件的交易，以便接收 通过数据引脚响应来自其他组件的警报信号，以确定事务的性质的状态请求，并且通过数据引脚向另一个组件响应状态请求来提供表示事务性质的状态。 提供警报信号，接收状态请求和提供状态可以参考时钟信号。 可以公开或要求保护其他实施例。

公开(公告)号：US20150199248A1

公开(公告)日：2015-07-16

申请号：US14668114

申请日：2015-03-25

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F11/22 ,  G06F13/42 ,  G06F11/10 ,  G06F13/364 ,  G06F11/07

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.

公开(公告)号：US20150120977A1

公开(公告)日：2015-04-30

申请号：US14537859

申请日：2014-11-10

Applicant: Intel Corporation

Inventor： Mikal C. Hunsaker ,  Su Wei Lim ,  Ricardo E. James

IPC: G06F13/42 ,  G06F13/364 ,  G06F1/24 ,  G06F1/06

CPC classification number: G06F13/364 ,  G06F1/06 ,  G06F1/24 ,  G06F11/0727 ,  G06F11/0745 ,  G06F11/1004 ,  G06F11/1072 ,  G06F11/221 ,  G06F11/2289 ,  G06F11/3027 ,  G06F13/00 ,  G06F13/122 ,  G06F13/1668 ,  G06F13/4068 ,  G06F13/4221 ,  G06F13/423 ,  G06F13/4234 ,  G06F13/4282 ,  G06F13/4291 ,  G11C29/52

Abstract: Component apparatuses with inter-component communication capabilities, and system having such component apparatuses are disclosed herein. In embodiments, such a component may include a number of control pins including a clock pin, a number of data pins, and a logic unit. The logic unit may be configured to receive a clock signal from another component through the clock pin, to provide an alert signal to the other component through a selected one of the control and data pins to initiate a transaction with the other component, to receive in response to the alert signal from the other component through the data pins a status request to determine nature of the transaction, and to provide in response to the status request to the other component through the data pins a status to indicate the nature of the transaction. The provision of the alert signal, the receipt of the status request and the provision of the status may be in reference to the clock signal. Other embodiments may be disclosed or claimed.